Cirrus Logic CS42L42 Manual page 10

PMU
Note 1
Battery
1.8 V 1.8 V/1.2 V
(3.0–5.0 V)
Applications
Processor
All external passive component
values shown are nominal.
Key for Capacitor Types Required:
Use low ESR, X7R/X5R capacitors
*
If no type symbol is shown next to a
capacitor, any type may be used.
Notes:
1. R and R values can be determined by the INT and WAKE pin specifications in
P_I P_W
2. HPSENSA and HPSENSB are supported only on the WLCSP package.
3. R values can be determined by the I
P_I2C
4. The headphone amplifier's output power and distortion ratings use the nominal capacitances shown. Larger capacitance reduces ripple on
the internal amplifiers' supplies and, in turn, reduces distortion at high-output power levels. Smaller capacitance may not reduce ripple
enough to achieve output power and distortion ratings. Because actual values of typical X7R/X5R ceramic capacitors deviate from nominal
values by a percentage specified in the manufacturer's data sheet, capacitors must be selected for minimum output power and maximum
distortion required. Higher value capacitors than those shown may be used, however lower value capacitors must not (values can vary from
the nominal by ±20%). See
5. Series resistance in the path of the power supplies must be avoided. Any voltage drop on VCP directly affects the negative charge-pump
supply (–VCP_FILT) and clips the audio output.
6. Lowering capacitance below the value shown affects PSRR, THD+N performance, ADC–DAC isolation and intermodulation, and
interchannel isolation and intermodulation.
DS1083F2
R
P_W
See
VL or VP
DIGLDO_PDN
and VL_SEL
Configurations
VL or VP 2.2 µF
R
P_I
Note 1
Optional Connections
2.2 µF 2.2 µF 2.2 µF
*
* *
Note 4
Note 5
2.2 µF
*
2.2 µF
*
4.7 µF
4.7 µF
*
*
Note 6
10 µF
*
Figure 2-2. Typical Connection Diagram for SoundWire
2 C pull-up resistance specification in
Section 2.1.2 for additional details.
CS42L42
_____
WAKE
RING_SENSE
VL_SEL
TIP_SENSE
DIGLDO_PDN
VL
HPOUTB
Headphone
VD_FILT HPOUTA
Output Filter
VA
HS3
HS4
HS3_REF
HS4_REF
INT
RESET
HSIN+
SCL
HSIN–
SDA
AD0
GNDHS
AD1
ASP_LRCK/FSYNC
ASP_SCLK/SWIRE_CLK
SWIRE_SD/ASP_SDIN
ASP_SDOUT
SWIRE_SEL
GNDD
GNDL
VCP
+VCP_FILT
SPDIF_TX
–VCP_FILT
GNDCP
FLYP
FLYC
FLYN
VP
HSBIAS_FILT
TSTI
HSBIAS_FILT_REF
FILT+
GNDA
Table
Table 3-24.
2 Typical Connections
Headset Connector
DIGLDO_PDN and VL_SEL
Configurations
DIGLDO_PDN = 0 (GNDD)
VL_SEL = 0 (GNDD)
1.2 V
0.1 µF
*
1 µF
*
DIGLDO_PDN = 0 (GNDD)
VL_SEL = 1 (3.0 to 5.0 V)
Battery
(VP = 3.0 to 5.0V)
1.8 V
Optical
0.1 µF
Transmitter
1.2 V
*
Module
1 µF
*
DIGLDO_PDN = 1 (3.0 to 5.0 V)
VL_SEL = 1 (3.0 to 5.0 V)
Battery
(VP = 3.0 to 5.0V)
1.8 V
0.1 µF
*
3-25.
CS42L42
VL_SEL
DIGLDO_PDN
VL
VD_FILT
VL_SEL
DIGLDO_PDN
VL
VD_FILT
VL_SEL
DIGLDO_PDN
VL
VD_FILT
10