Cirrus Logic CS42L42 Manual page 94

Example 5-3. SoundWire Power-Up Sequence (Cont.)
S T
TEP ASK
10 Power up the codec.
11 Configure Ports 1-14 common settings
11.1 Ports 1-14 Control
11.2 Ports 1-14 Block Control DP1-14 Block Control 1
11.3 Port 1-14 Sample Control
1—Bank 1
11.4 Port 1-14 Sample Control
2—Bank 1
11.5 Ports 1-14 Horizontal
Control—Bank 1
11.6 Ports 1-14 Block
Control 3—Bank 1
12 Configure Ports 1 (ADC)
12.1 Port 1 Offset Control 1—
Bank 1
12.2 Port 1 Offset Control 2—
Bank 1
12.3 Port 1 Prepare Control
12.4 Read Port 1 prepare
Status. Repeat until
value is 0x00.
12.5 Port 1 Channel Enable—
Bank 1
13 Configure Port 2 (headphone data)
13.1 Port 2 Offset Control 1—
Bank 1
13.2 Port 2 Offset Control 2—
Bank 1
13.3 Port 2 Prepare Control
13.4 Read Port 2 Prepare
Status. Repeat until
value is 0x00.
13.5 Port 2 Channel Enable—
Bank 1
DS1083F2
R /B
EGISTER IT
Power Down Control 1. 0x1101
ASP_DAO_PDN
ASP_DAI_PDN
MIXER_PDN
EQ_PDN
HP_PDN
ADC_PDN
Reserved
PDN_ALL
DP1-14 Port Control (Section 7.2.3). 0x0F02
Reserved
INVERT_BANK
PORT_DATA_MODE
Reserved
(Section
Reserved
WORD_LENGTH
DP1-14 Sample Control 1 (Banked,
0x0F32
SAMPLE_INTERVAL_LOW
DP1-14 Sample Control 2 (Banked,
0x0F33
SAMPLE_INTERVAL_HIGH
DP1-14 Horizontal Control (Banked,
0x0F36
HSTART
HSTOP
DP1-14 Block Control 3 (Banked,
0x0F37
Reserved
BLOCK_PACKING_MODE
DP1 Offset Control 1 (Banked, Section
OFFSET1
DP1 Offset Control 2 (Banked, Section
OFFSET2
DP1 Prepare Control (Section 7.2.6). 0x0105
Reserved
PREPARE_CHANNEL2
PREPARE_CHANNEL1
DP1 Prepare Status (Section 7.2.5). 0x0104
Reserved
NOT_FINISHED_CHANNEL2
NOT_FINISHED_CHANNEL1
DP1 Channel Enable (Banked,
Reserved
CHANNEL_EN2
CHANNEL_EN1
DP2 Offset Control 1 (Banked, Section
OFFSET1
DP2 Offset Control 2 (Banked, Section
OFFSET2
DP2 Prepare Control (Section 7.2.6). 0x0205
Reserved
PREPARE_CHANNEL2
PREPARE_CHANNEL1
DP2 Prepare Status (Section 7.2.5). 0x0204
Reserved
NOT_FINISHED_CHANNEL2
NOT_FINISHED_CHANNEL1
DP2 Channel Enable (Banked,
Reserved
CHANNEL_EN2
CHANNEL_EN1
F V
IELDS ALUE
0xD2
1
1
0
1
0
0
1
0
0x00
000
0
00
00
7.2.4). 0x0F03 0x17
00
01 0111
Section 7.2.8). 0xFF
1111 1111 Sample interval = 512
Section 7.2.9). 0x01
0000 0001 Sample interval = 512
Section 7.2.12). 0x17
0001
0111
Section 7.2.13). 0x00
0000 000
0
7.2.10). 0x0134 0x00
0000 0000 Block offset = 0
7.2.11). 0x0135 0x00
0000 0000 Block offset = 0
0x01
0000 00
0
1
0x00
0000 00
0
0
Section 7.2.7). 0x0130 0x01
0000 00
0
1
7.2.10). 0x0234 0x1C
0001 1100 Block offset = 28
7.2.11). 0x0235 0x00
0000 0000 Block offset = 28
0x03
0000 00
1
1
0x00
0000 00
0
0
Section 7.2.7). 0x0230 0x03
0000 00
1
1
CS42L42
5.3 SoundWire Power Sequences
D
ESCRIPTION
ASP output path is powered down.
ASP input path is powered down.
Mixer is powered up.
Equalizer is powered down
HPOUT is powered up.
ADC is powered up.
—
Codec is powered up.
—
Use bank as directed in the control word
Normal port mode
—
—
24-bit data
Subframe begins in Column 1
Subframe ends in Column 7
—
Block-per-Port Mode
—
Channel deactivated
Channel commanded to prepare for activity
—
Channel finished
Channel finished
—
Channel disabled
Channel enabled
—
Channel commanded to prepare for activity
Channel commanded to prepare for activity
—
Channel finished
Channel finished
—
Channel enabled
Channel enabled
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