Cirrus Logic CS42528-DQZ Manuals

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Cirrus Logic CS42528-DQZ Manual (91 pages)

114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

Brand: Cirrus Logic | Category: Conference System | Size: 0 MB

Table of Contents
2
Characteristics and Specifications
7
Specified Operating Conditions
7
Absolute Maximum Ratings
7
Analog Input Characteristics
8
A/D Digital Filter Characteristics
9
Analog Output Characteristics
10
D/A Digital Filter Characteristics
11
Switching Characteristics
12
Figure 1. Serial Audio Port Master Mode Timing
12
Figure 2. Serial Audio Port Slave Mode Timing
12
Switching Characteristics - Control Port - I C Format
13
Figure 3. Control Port Timing - I 2 C Format
13
Switching Characteristics - Control Port - SPI TM Format
14
Figure 4. Control Port Timing - SPI Format
14
DC Electrical Characteristics
15
Digital Interface Characteristics
16
Pin Descriptions
17
Typical Connection Diagram
20
Figure 5. Typical Connection Diagram
20
Applications
21
Overview
21
Analog Inputs
21
Line Level Inputs
21
Figure 6. Full-Scale Analog Input
21
High Pass Filter and DC Offset Calibration
22
Analog Outputs
22
Line Level Outputs and Filtering
22
Interpolation Filter
22
Figure 7. Full-Scale Output
22
Digital Volume and Mute Control
23
ATAPI Specification
23
Figure 8. ATAPI Block Diagram (X = Channel Pair 1, 2, 3, 4)
23
S/PDIF Receiver
24
8:2 S/PDIF Input Multiplexer
24
Error Reporting and Hold Function
24
Channel Status Data Handling
24
User Data Handling
24
Non-Audio Auto-Detection
24
Clock Generation
25
PLL and Jitter Attenuation
25
Figure 9. CS42528 Clock Generation
25
OMCK System Clock Mode
26
Master Mode
26
Slave Mode
26
Table 1. Common OMCK Clock Frequencies
26
Table 2. Common PLL Output Clock Frequencies
26
Table 3. Slave Mode Clock Ratios
26
Digital Interfaces
27
Serial Audio Interface Signals
27
Table 4. Serial Audio Port Channel Allocations
27
Serial Audio Interface Formats
29
Figure 10. I 2 S Serial Audio Formats
29
Figure 11. Left Justified Serial Audio Formats
30
Figure 12. Right Justified Serial Audio Formats
30
Figure 13. One Line Mode #1 Serial Audio Format
31
Figure 14. One Line Mode #2 Serial Audio Format
31
ADCIN1/ADCIN2 Serial Data Format
32
Figure 15. ADCIN1/ADCIN2 Serial Audio Format
32
One Line Mode(OLM) Configurations
33
OLM Config #1
33
Figure 16. OLM Configuration #1
33
OLM Config #2
34
Figure 17. OLM Configuration #2
34
OLM Config #3
35
Figure 18. OLM Configuration #3
35
OLM Config #4
36
Figure 19. OLM Configuration #4
36
OLM Config #5
37
Figure 20. OLM Configuration #5
37
Control Port Description and Timing
38
SPI Mode
38
Figure 21. Control Port Timing in SPI Mode
38
I 2 C Mode
39
Figure 22. Control Port Timing, I C Write
39
Figure 23. Control Port Timing, I C Read
39
Interrupts
40
Reset and Power-Up
40
Power Supply, Grounding, and PCB Layout
40
Register Quick Reference
42
Register Description
47
Memory Address Pointer (MAP)
47
Chip I.D. and Revision Register (Address 01H) (Read Only)
47
Power Control (Address 02H)
48
Functional Mode (Address 03H)
49
Interface Formats (Address 04H)
50
Table 5. DAC De-Emphasis
50
Table 6. Receiver De-Emphasis
50
Table 7. Digital Interface Formats
51
Table 8. ADC One-Line Mode
51
Table 9. DAC One-Line Mode
51
Misc Control (Address 05H)
52
Clock Control (Address 06H)
53
Table 10. RMCK Divider Settings
53
Table 11. OMCK Frequency Settings
54
Table 12. Master Clock Source Select
54
OMCK/PLL_CLK Ratio (Address 07H) (Read Only)
55
RVCR Status (Address 08H) (Read Only)
55
Table 13. AES Format Detection
55
Burst Preamble PC and PD Bytes (Addresses 09H - 0Ch)(Read Only)
56
Table 14. Receiver Clock Frequency Detection
56
Volume Transition Control (Address 0Dh)
57
Channel Mute (Address 0Eh)
59
Volume Control (Addresses 0Fh, 10H, 11H, 12H, 13H, 14H, 15H, 16H)
59
Channel Invert (Address 17H)
59
Table 15. Example Digital Volume Settings
59
Mixing Control Pair 1 (Channels A1 & B1)(Address 18H)
60
Mixing Control Pair 2 (Channels A2 & B2)(Address 19H)
60
Mixing Control Pair 3 (Channels A3 & B3)(Address 1Ah)
60
Mixing Control Pair 4 (Channels A4 & B4)(Address 1Bh)
60
Table 16. ATAPI Decode
61
ADC Left Channel Gain (Address 1Ch)
62
ADC Right Channel Gain (Address 1Dh)
62
Receiver Mode Control (Address 1Eh)
62
Table 17. Example ADC Input Gain Settings
62
Receiver Mode Control 2 (Address 1Fh)
63
Table 18. TXP Output Selection
63
Interrupt Status (Address 20H) (Read Only)
64
Table 19. Receiver Input Selection
64
Interrupt Mask (Address 21H)
65
Interrupt Mode MSB (Address 22H) Interrupt Mode LSB (Address 23H)
65
Channel Status Data Buffer Control (Address 24H)
66
Receiver Channel Status (Address 25H) (Read Only)
67
Table 20. Auxiliary Data Width Selection
67
Receiver Errors (Address 26H) (Read Only)
68
Receiver Errors Mask (Address 27H)
69
Mutec Pin Control (Address 28H)
69
Rxp/General Purpose Pin Control (Addresses 29H to 2Fh)
70
Q-Channel Subcode Bytes 0 to 9 (Addresses 30H to 39H) (Read Only)
72
C-Bit or U-Bit Data Buffer (Addresses 3Ah to 51H) (Read Only)
72
Parameter Definitions
73
References
74
Package Dimensions
75
Thermal Characteristics
75
Appendix A: External Filters
76
ADC Input Filter
76
DAC Output Filter
76
Figure 24. Recommended Analog Input Buffer
76
Figure 25. Recommended Analog Output Buffer
76
Appendix B: S/Pdif Receiver
77
Error Reporting and Hold Function
77
Channel Status Data Handling
77
Channel Status Data E Buffer Access
78
One Byte Mode
78
Two Byte Mode
78
Figure 26. Channel Status Data Buffer Structure
78
Serial Copy Management System (SCMS)
79
User (U) Data E Buffer Access
79
Non-Audio Auto-Detection
79
Format Detection
79
Appendix C: Pll Filter
80
Figure 27. PLL Block Diagram
80
External Filter Components
81
General
81
Jitter Attenuation
81
Figure 28. Jitter Attenuation Characteristics of PLL
81
Table 21. PLL External Component Values
81
Capacitor Selection
82
Circuit Board Layout
82
Figure 29. Recommended Layout Example
82
Appendix D: External Aes3/Spdif/Iec60958 Receiver Components
83
AES3 Receiver External Components
83
Figure 30. Consumer Input Circuit
83
Figure 31. S/PDIF MUX Input Circuit
83
Figure 32. TTL/CMOS Input Circuit
83
Appendix E: Adc Filter Plots
84
Figure 33. Single Speed Mode Stopband Rejection
84
Figure 34. Single Speed Mode Transition Band
84
Figure 35. Single Speed Mode Transition Band (Detail)
84
Figure 36. Single Speed Mode Passband Ripple
84
Figure 37. Double Speed Mode Stopband Rejection
84
Figure 38. Double Speed Mode Transition Band
84
Figure 39. Double Speed Mode Transition Band (Detail)
85
Figure 40. Double Speed Mode Passband Ripple
85
Figure 41. Quad Speed Mode Stopband Rejection
85
Figure 42. Quad Speed Mode Transition Band
85
Figure 43. Quad Speed Mode Transition Band (Detail)
85
Figure 44. Quad Speed Mode Passband Ripple
85
Appendix F: Dac Filter Plots
86
Figure 45. Single Speed (Fast) Stopband Rejection
86
Figure 46. Single Speed (Fast) Transition Band
86
Figure 47. Single Speed (Fast) Transition Band (Detail)
86
Figure 48. Single Speed (Fast) Passband Ripple
86
Figure 49. Single Speed (Slow) Stopband Rejection
86
Figure 50. Single Speed (Slow) Transition Band
86
Figure 51. Single Speed (Slow) Transition Band (Detail)
87
Figure 52. Single Speed (Slow) Passband Ripple
87
Figure 53. Double Speed (Fast) Stopband Rejection
87
Figure 54. Double Speed (Fast) Transition Band
87
Figure 55. Double Speed (Fast) Transition Band (Detail)
87
Figure 56. Double Speed (Fast) Passband Ripple
87
Figure 57. Double Speed (Slow) Stopband Rejection
88
Figure 58. Double Speed (Slow) Transition Band
88
Figure 59. Double Speed (Slow) Transition Band (Detail)
88
Figure 60. Double Speed (Slow) Passband Ripple
88
Figure 61. Quad Speed (Fast) Stopband Rejection
88
Figure 62. Quad Speed (Fast) Transition Band
88
Figure 63. Quad Speed (Fast) Transition Band (Detail)
89
Figure 64. Quad Speed (Fast) Passband Ripple
89
Figure 65. Quad Speed (Slow) Stopband Rejection
89
Figure 66. Quad Speed (Slow) Transition Band
89
Figure 67. Quad Speed (Slow) Transition Band (Detail)
89
Figure 68. Quad Speed (Slow) Passband Ripple
89
Table 22. Revision History
90

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