S/Pdif Tx Port - Cirrus Logic CS42L42 Manual

Name Direction
LRCK Early Tx/Rx Set when the number of SCLK periods per LRCK phase (high or low) is less than the
expected count as determined by x_LCPR and x_LCHI.
Note: The Rx LRCK early interrupt status is set during the first receive LRCK early event.
Subsequent receive LRCK early events are indicated only if valid LRCK transitions are
detected.
LRCK Late Tx/Rx Set when the number of SCLK periods per LRCK phase (high or low) is greater than the
expected count as determined by x_LCPR and x_LCHI.
No LRCK Tx/Rx Note: Set when the number of SCLK periods counted exceeds twice the value of LRCK
period (x_LCPR) without an LRCK edge. The Tx No LRCK interrupt status is set during
the first instance of a no-transmit LRCK condition. Subsequent no-transmit LRCK
conditions are not indicated until after valid LRCK transitions are detected.
SM Error Tx Set if the transmit state machine cannot retrieve data from output buffers (analogous to Rx
Request Overload). If all channel registers are properly configured, this status is never set.
Note: The interrupt status is set during the first transmit SM error event. Subsequent SM
error events are not indicated until after the FIFO exits the overflow state.
4.9.7 Recommended Serial-Port Power-Up and Power-Down Strategies
Although multiple safeguards and controls are implemented to prevent a run on the FIFOs involved in passing data from
the input port to the output port, the following power-up sequence is recommended.
1. Configure all playback/record channel characteristics—bit resolution, channel select, source (DAI/DAO or SW),
native/isochronous, sample rates, etc.
2. Power up playback, record path, and ASRCs.
3. Release the PDN_ALL bit.
4. Power up the serial ports (DAI/DAO).
The following power-down sequence is recommended:
1. Power down the playback and record paths.
2. Power down the serial ports.

4.10 S/PDIF Tx Port

The S/PDIF output port is integrated to provide a pass-through of encoded (e.g., AC3) or PCM data from the serial audio
ports to an external optical driver. The S/PDIF port does not support isochronous audio streams.
4.10.1 S/PDIF Pass-Through Transmission
The CS42L42 S/PDIF transmitter performs pass-through retransmission of stereo samples that are generated on an
external device and transported over the TDM or SoundWire port. This transmitter can be programmed to retransmit any
two of the 16-, 20-, 24-, or 32-bit S/PDIF encoded samples from the serial port by programming
(note that this is RX0 Channels 1–4 and RX1 Channels 1 and 2, see
S/PDIF rates are 32, 44.1, 48, 88.2, 96, 176.4, and 192 kHz and are configured through
The CS42L42 does not decode or interpret samples chosen for retransmission. Additionally, the S/PDIF path does not
incorporate any SRCs in the data path.
When the data source comes from the TDM source, the CS42L42 selects between data from the DAI0 or DAI1 as follows:
• If DAI0, configure SPDIF_CHA_SEL/SPDIF_CHB_SEL
S/PDIF inputs. ASP_RX0_2FS
• If ASP_RX1_2FS = 1 (see
at different rates, the S/PDIF transmit port gets data from the DAI1 and ignores data from the DAI0. Channel 0 of
DAI1 maps to left channel and Channel 1 of DAI1 maps to right channel.
If the data source comes from the SoundWire port, signals are retimed and passed to the S/PDIF transmit port.
DS1083F2
Table 4-18. Serial Port Status (Cont.)
Description
= 0 (see p. 164).
p. 164), which means there is simultaneous operation on both the TDM and S/PDIF ports
Section 5
p. 165) an SPDIF_RES
d
(see p. 159) to map any of the four TDM slots (0–3) to the
CS42L42
4.10 S/PDIF Tx Port
Register Reference
ASPRX_EARLY p. 140
ASPTX_EARLY p. 141
ASPRX_LATE p. 140
ASPTX_LATE p. 141
ASPRX_NOLRCK p. 140
ASPTX_NOLRCK p. 141
ASPTX_SMERROR p. 141
gives detailed sequences.
ASP_RX0_CH1_RES
(see p. 160). The supported
SPDIF_TX_STAT (see p. 162).
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