Cirrus Logic CS42L42 Manual page 6

CSP
Pin Name
Pin #
SDA
A1
SPDIF_TX A6
SWIRE_SEL D3
VL_SEL C4
C6
WAKE
–VCP_FILT G6
+VCP_FILT E6
FLYC
F7
FLYN G7
FLYP E7
FILT+ C1
VA B1
VCP
D6
VD_FILT
A7
VL
A3
VP
D7
GNDA C2
GNDL B3
GNDHS G1
GNDCP F6
GNDD B6
TSTI D2, C7
1.The power supply is determined by ADPTPWR setting (see
ADPTPWR = 111 (Adapt-to-Signal Mode).
DS1083F2
Table 1-1. Pin Descriptions (Cont.)
QFN Power
I/O
Supply
Pin #
36 2
VL I/O I C Input/Output. I
45 VL O S/PDIF Audio Serial Data Output. Serial data
output for S/PDIF interface.
40 VL I SoundWire Select. SoundWire interface selection
input. Defines the serial and audio interface type. If
asserted, SoundWire is the control and audio
interface, otherwise I
used for audio data.
48
VP I VL Supply Voltage Select. Select for VL power
supply voltage level. Connect to VP for 1.8-V VL
supply, connect to GNDD for 1.2-V VL supply
3 VP O Wake up. Programmable, open-drain, active-low
output. This outputs the state of the Mic S0 or HP
wake detect.
13
VCP/ O Inverting Charge Pump Filter Connection. Power
VP supply for the inverting charge pump that provides
1
the negative rail for the HP amplifier.
10 VCP/ O Step Down Charge Pump Filter Connection.
1
VP Power supply for the step down charge pump that
provides the positive rail for the HP amplifier.
9
VCP/ O Charge Pump Cap Common Node. Common
VP 1 positive node for the HP amplifiers' step-down and
inverting charge pumps' flying capacitors.
11
VCP/ O Charge Pump Cap Negative Node. Negative node
VP for the inverting charge pump's flying capacitor.
1
8
VCP/ O Charge Pump Cap Positive Node. Positive node for
VP HP amps' step-down charge pump's flying capacitor.
1
32
VA I Positive Voltage Reference. Positive reference
voltage for internal sampling circuits.
33
N/A I Analog Power Supply. Power supply for the internal
analog section.
7
N/A I Charge Pump Power. Power supply for the internal
HP amplifiers charge pump.
47
N/A I 1.2-V Digital Core Power Supply. Power supply for
internal digital logic.
39
N/A I I/O Power Supply. Power supply for external
interface and internal digital logic.
6
N/A I High Voltage Interface Supply. Power supply for
high voltage interface.
31
N/A I Analog Ground. Ground reference for the internal
analog section.
38
N/A I Digital Ground. Ground reference for interface
section.
25
N/A I Headset Ground. Ground reference for the internal
analog section.
12
N/A I Charge Pump Ground. Ground reference for the
internal HP amplifiers charge pump.
46 N/A I Digital Ground. Ground reference for the internal
digital circuits.
— N/A I Test input. Connect to GNDA.
Section
Pin Description
2
C input and output.
2 C is control and TDM/I 2
Charge Pump
Power
Ground
Test
7.14.1). VP is used if ADPTPWR = 001 (VP_CP Mode) or when necessary for
1.3 Pin Descriptions
Internal
Driver
Connection
— CMOS
open-drain
output
— CMOS
output
— —
S is
— —
— Hi-Z,
CMOS
open-drain
output
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
CS42L42
State at
Receiver
Reset
Hysteresis Input
on CMOS
input
— Output
Hysteresis Input
on CMOS
input
Hysteresis Input
on CMOS
input
— Output
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
6