Cirrus Logic CS42L42 Manual page 55

Field Command
RegAddr[15:0] Read/
Write
RegData Read
RegData Write
StaticSync All
PhySync All
DynamicSync[3:0] All
PAR All
NAK All
ACK All
4.8.4 Register Access Response
The SoundWire slave provides a response to each command in the Control Word NAK and ACK fields. A component of
the response is derived from the result of the register access command, as listed in
Command
Response NAK ACK
(Priority Order)
COMMAND_ 1 0
FAIL
COMMAND_ 0 0
IGNORED
COMMAND_ 0 1
OK
A command response to register access restrictions does not depend on the data value being written, but is governed by
whether the read or write access is allowed to that address. Writing an unsupported value to a register address does not
cause the write command to be rejected. If multiple entries of
that triggers a COMMAND_FAIL overrides a COMMAND_IGNORED or COMMAND_OK. Conditions that trigger a
COMMAND_IGNORED override conditions that trigger COMMAND_OK.
DS1083F2
Table 4-8. Control Word Bit Slot Fields (Cont.)
Bit Slot Owner
Command owner Register address identifying which register is being accessed by the command. Bits 14:0
contain the address.
Addressed slave Register data sent from the addressed device (slave or master) to command owner
(master or monitor)
Command owner Register data sent from command owner (master or monitor) to the addressed device
(slave or master)
Master Fixed pattern 1011_0001 that facilitates the slave synchronizing to the bit stream and
determining frame shape.
Master Identifies whether the physical layer interface is running in Basic PHY or High PHY Mode.
0 Basic PHY This device supports only Basic PHY.
1 High PHY
Master Cyclic pattern that facilitates the slave synchronizing to the bit stream and determining
frame shape.
Command owner Parity checksum generated by the owner of the command fields (master or monitor),
checked by the other interfaces (slave, and monitor or master).
All attached devices Negative acknowledge
All attached devices Positive acknowledge
Table 4-9. Command Response
SoundWire
Address Range
(RegAddr[15:0])
All • Parity error
• A bus clash is detected in the Control Word, except for shared bits: PREQ, NAK, ACK, and
shared group read data or slave status (when DevAddr = {0,12,13,15}) where bus clash is
expected and not reported.
0x1000–0xFFFF • APB bridge access is rejected because the bridge was busy with a previous access and
could not accept a new one.
Note: This behavior is not compliant with the The MIPI SoundWire Specification 1.0.
All • Slave is not attached to the SoundWire Bus.
• Response to a Ping command
• Response to reserved opcodes
• Response to Read/Write command whose DevAddr value does not address this slave
0x0000–0x0FFF • Access to an address where no register is implemented, including any register address
associated with the unimplemented data ports (Ports 4–14).
• Read from address containing only write-only register bits.
• Write to address containing only read-only register bits
• Read from Port 15 group alias
• Read of any slave control port (SCP) device ID register if the slave is out of enumeration
• Write to the SCP device number register if the slave is out of enumeration
0x0000–0x0FFF • A read or write access to an existing register is not constrained by the conditions above
0x1000–0xFFFF • An APB bridge access was accepted and a COMMAND_OK response acknowledges that
the internal memory access has begun. This response does not convey whether the access
was to an implemented address or whether the address is valid for the command.
Note: For accesses within the range 0x1000–0x1FFF, the COMMAND_OK response is
specific to the CS42L42. The MIPI SoundWire Specification 1.0 requires a COMMAND_
IGNORED response to be returned instead of the COMMAND_OK.
Description
Section 4.8.9 describes how RegAddr is formed.
Table
Conditions
Section 4.8.12 describes the APB.
Table 4-9 apply to the same SoundWire frame, any condition
CS42L42
4.8 SoundWire Interface
4-9.
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