Characteristics And Specifications - Cirrus Logic CS42L42 Manual

3 Characteristics and Specifications

Table 3-1 defines parameters as they are characterized in this section.
Table 3-1. Parameter Definitions
Parameter
Dynamic range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. A
signal-to-noise ratio measurement over the specified bandwidth made with a –60 dB signal; 60 dB is added to resulting
measurement to refer the measurement to full scale. This technique ensures that distortion components are below the noise
level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17–1991, and the Electronic Industries Association of Japan, EIAJ CP–307. Dynamic range is expressed in decibel units.
Idle channel The rms value of the signal with no input applied (properly back-terminated analog input, digital zero, or zero modulation input).
noise Measured over the specified bandwidth.
Interchannel A measure of cross talk between the left and right channel pairs. Interchannel isolation is measured for each channel at the
isolation converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Interchannel
isolation is expressed in decibel units.
Load The recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal
resistance and integrity. The load capacitance effectively moves the band-limiting pole of the amp in the output stage. Increasing load
capacitance capacitance beyond the recommended value can cause the internal op-amp to become unstable.
Offset error The deviation of the midscale transition (111...111 to 000...000) from the ideal.
Output offset The DC offset voltage present at the amplifier's output when its input signal is in a mute state. The offset exists due to CMOS
voltage process limitations and is proportional to analog volume settings. When measuring the offset out the headphone amplifier, the
headphone amplifier is ON.
Total harmonic The ratio of the rms sum of distortion and noise spectral components across the specified bandwidth (typically 20 Hz–20 kHz)
distortion + relative to the rms value of the signal. THD+N is measured at –1 and –20 dBFS for the analog input and at 0 and –20 dB for
noise (THD+N) the analog output, as suggested in AES17–1991 Annex A. THD+N is expressed in decibel units.
Table 3-2. Recommended Operating Conditions
Test conditions: GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground.
DC power Charge pump
supply
LDO regulator for digital
Serial interface control port
and S/PDIF transmitter
Analog
Battery supply
External voltage
applied to pin 4,5
Ambient temperature
1.Device functional operation is guaranteed within these limits; operation outside them is not guaranteed or implied and may reduce device reliability.
2.If DIGLDO_PDN is deasserted, no external voltage must be applied to VD_FILT.
3.Although device operation is guaranteed down to 2.5 V, device performance is guaranteed only down to 3.0 V. The following are affected when
VP < 3.0 V: HSBIAS, charge pump LDO, TIP_SENSE threshold, RING_SENSE threshold.
4.The maximum over/undervoltage is limited by the input current.
5.Table 1-1 lists the power supply domain in which each CS42L42 pin resides.
6.±VCP_FILT is specified in Table
Table 3-3. Absolute Maximum Ratings
Test conditions: GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground.
DC power supply
Input current 1
Ambient operating temperature (power applied)
Storage temperature
Caution: Stresses beyond "Absolute Maximum Ratings" levels may cause permanent damage to the device. These levels are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in
Conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1.Any pin except supply pins. Transient currents of up to ±100 mA on analog input pins do not cause SCR latch-up.
DS1083F2
Parameters
2
DIGLDO_PDN = 0 and VL_SEL = 0
DIGLDO_PDN = 0 and VL_SEL = 0
±VCP_FILT domain pins
3-16.
Parameters
Charge pump, LDO, serial/control, analog (see
Definition
Symbol
VCP
VD_FILT
VL
VL_SEL = 1 VL
VA
VP
TIP_SENSE pin V
INHI
6 V
VCPF
VL domain pins V
VL
VA domain pins V
VA
VP domain pins V
VP
T
A
Section 4.15
Digital core
Battery
3 Characteristics and Specifications
Minimum 1 Maximum
1.66 1.94
1.10 1.30
1.10 1.30
1.66 1.94
1.66 1.94
2.50 3 5.25
–VCP_FILT – 0.3 VP + 0.3
–VCP_FILT – 0.3 +VCP_FILT + 0.3
–0.3 VL + 0.3
–0.3 VA + 0.3
–0.3 VP + 0.3
–40 +85
Symbol Minimum Maximum Unit
)
VL, VA, VCP –0.3
VD_FILT –0.3
VP –0.3
I
—
in
T –50
A
T –65
stg
Table 3-2, "Recommended Operating
CS42L42
1 Unit
V
V
V
V
V
V
V
V
V
V
V
C
2.33 V
1.55
V
6.3 V
±
10 mA
+115 °C
+150 °C
12