Cirrus Logic CS42L42 Manual page 131

Bits Name
2 ADC_ ADC power down
PDN
0 Powered up. The ADC is powered up.
1 (Default) The ADC is powered down.
1 — Reserved
0 PDN_ Codec power down. Configures the entire codec's power state except for PLL_START and SPDIF_TX_PDN (which is not
affected in order to support Keep-Alive Mode). After power up (PDN_ALL: 1  0), individual subblocks are powered according
ALL
to power-control programming. This bit is affected by
Note: The SRC power-down state depends on the
0 Powered up, per the individual x_PDN controls
1 (Default) Powered down. PDN_ALL must not be set without first enabling LATCH_TO_VP. After PDN_ALL is set and the
entire codec is powered down, PDN_DONE is set, indicating that SCLK can be removed.
7.4.2 Power Down Control 2
R/W
7
Default 1
Bits Name
7:5 — Reserved
4 DISCHARGE_ Discharge FILT+ capacitor. Configures the state of the FILT+ pin internal clamp. Before setting this bit, ensure that the
FILT+ VD_FILT device input is connected to a supply, as shown in
0 (Default) FILT+ is not clamped to ground.
1 FILT+ is clamped to ground. This must be set only if PDN_ALL = 1. Discharge time with an external 2.2-µF
capacitor on FILT+ is ~46 ms.
3 SRC_PDN_ SRC power down override. Configures the SRCs' power states.
OVERRIDE
0 (Default) Power state control for the DAC and ADC SRCs, which are controlled by the following smart logic:
• DAC SRCs are off if SRC_BYPASS_DAC = 1.
• ADC SRC is off if SRC_BYPASS_ADC = 1.
• If PDN_ALL = 1, all SRCs are off.
• If PDN_ALL = 0 and the respective ADC or DAC bypass bits = 0, the following controls each SRC's power state:
—If SWIRE _SEL pin = VL, all SRCs are ON
—If SWIRE_SEL pin = GNDL the following applies:
1 DAC SRCs are controlled by DAC_SRC_PDNB and the ADC SRC is controlled by ADC_SRC_PDNB.
2 ASP_DAI1_ ASP DAI1power down. This applies only to the S/PDIF port.If ASP_DAI_PDN is set, DAI1 is also powered down
PDN regardless of this register setting.
0 ASP power up
1 (Default) ASP power down
1 DAC_SRC_ DAC SRC power down. Configures the DAC ASP power state if SRC_PDN_OVERRIDE = 1.
PDNB
0 (Default) Power down
1 Power up audio DAC SRC only
0 ADC_SRC_ ADC SRC power down. Configures the ADC SRC power state if SRC_PDN_OVERRIDE = 1.
PDNB
0 (Default) Power down
1 Power up audio ADC SRC only
DS1083F2
6 5
DISCHARGE_
—
0 0
–If DAI0 is enabled, the DAC SRCs are powered up.
–If DAO is enabled, the ADC SRC is powered up.
Description
LATCH_TO_VP (see p. 150).
SRC_PDN_OVERRIDE setting (see
4 3
SRC_PDN_
ASP_DAI1_PDN
FILT+ OVERRIDE
0 0
Description
Table 3-2.
7.4 Power Down and Headset Detects
p. 131).
2 1
DAC_SRC_
PDNB
1 0
CS42L42
Address 0x1102
0
ADC_SRC_
PDNB
0
131