Cirrus Logic CS42L42 Manual page 58

Block per Channel
Ch0 [3:0]
Vertical spacing that may be used by unrelated ports
Ch1 [3:0]
• Payload window—A contiguous set of columns in the frame, within which data is transferred for the respective port
defined by the HSTART/HSTOP fields. Transport windows may overlap, with different data streams transferred in
different bit slots.
The payload subwindow is the subset of a payload window where the port's data resides, as controlled by the
block-spacing mode.
• There are two types of payload data:
— Normal payload (isochronous payload streams)
— Flow-controlled (asynchronous payload streams)—Not supported on the CS42L42.
4.8.8 Prepare/Enable Control
The programming model of the state diagram of
requires the following procedure to enable the channel:
1. The master first prepares a channel by setting the channel's
If the channel is running and ready to transfer data on the SoundWire bus, data-path logic within the chip sets the
input port STAT_PORT_READY
2. The master waits until it reads the corresponding
3. The master sets the
4. Master initiates a bank switch to enable the channel set in Step 3 by writing to the inactive bank SCP frame control
register.
5. Data transfer on the SoundWire bus begins in the next frame after the bank switch.
It would be invalid programming for the master to set CHANNEL_EN without waiting for the DPn_PREPARE_STATUS bit
to indicate that the channel is ready for operation. Operation cannot be guaranteed in this case.
DS1083F2
Ch0 [15:10]
Ch0 [9:4]
↑
↓
Ch1 [15:10]
Ch1 [9:4]
Figure 4-26. Block Packing Mode
Fig. 4-27
(see p. 123). This value is reflected in the DPn prepare status register (see
CHANNEL_ENx bit (see p.
Ch0 [3:0]
Ch1 [1:0]
must be followed to enable each channel within a port. This
PREPARE_CHANNELx
NOT_FINISHED_CHANNELx
125) of the inactive bank.
4.8 SoundWire Interface
Block per Port
Ch0 [15:10]
Ch0 [9:4]
Ch1 [15:14]
Ch1 [13:18]
Ch1 [7:2]
register bit (see
status bit (see p. 125) as cleared.
CS42L42
p. 125).
p. 125).
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