Cirrus Logic CS42L42 Manual page 147

7.7.2 PLL Division Fractional Bytes 0–2
R/W
7
0x1502
0x1503
0x1504
Default
0
Bits Name
7:0 PLL_DIV_ PLL fractional portion of divide ratio LSB. See
FRAC[7:0] portion: This is LSB byte; e.g., 0xFF means (2
0000 0000 (Default)
7:0 PLL_DIV_ PLL fractional portion of divide ratio middle byte; e.g., 0xFF means (2
FRAC[15:8]
0000 0000 (Default)
7:0 PLL_DIV_ PLL fractional portion of divide ratio MSB; e.g., 0xFF means (2
FRAC[23:16]
0000 0000 (Default)
7.7.3 PLL Division Integer
R/W
7
Default 0
Bits Name
7:0 PLL_DIV_INT PLL integer portion of divide ratio. Integer portion of PLL feedback divider. See
0100 0000 (Default)
7.7.4 PLL Control 3
R/W
7
Default 0
Bits Name
7:0 PLL_ Final PLL clock output divide value. See
DIVOUT
0001 0000 (Default)
7.7.5 PLL Calibration Ratio
R/W
7
Default 1
Bits Name
7:0 PLL_CAL_ PLL calibration ratio. See
RATIO
1000 0000 (Default)
7.7.6 PLL Control 4
R/W
7
Default 0
Bits Name
7:2 — Reserved
1:0 PLL_ PLL bypass mode. Configures 500/512 and 1029/1024 factor bypasses. See
MODE 00 Unsupported
01 500/512 only (1029/1024 bypassed)
DS1083F2
6 5
0 0
6 5
1 0
6 5
0 0
Section 4.7.3
6 5
0 0
Section 4.7.3 for configuration details. Target value for PLL VCO calibration.
6 5
—
0 0
10 1029/1024 only (500/512 bypassed)
11 (Default) Both bypassed
4 3
PLL_DIV_FRAC[7:0]
PLL_DIV_FRAC[15:8]
PLL_DIV_FRAC[23:16]
0 0
Description
Section 4.7.3 for details. There are 3 bytes of PLL feedback divider fraction
–17 –18 –24
+ 2 + ...+2 )
–9 + 2
–1 + 2 –2 + ...+2
4 3
PLL_DIV_INT
0 0
Description
4 3
PLL_DIVOUT
1 0
Description
for configuration details.
4 3
PLL_CAL_RATIO
0 0
Description
4 3
0 0
Description
Section 4.7.3
7.7 Fractional-N PLL Registers
Address 0x1502–0x1504
2 1
0 0
–10 + ...+2 –16 ). See Section 4.7.3
–8 ). See Section 4.7.3 for details.
Address 0x1505
2 1
0 0
Section 4.7.3 for details.
Address 0x1508
2 1
0 0
Address 0x150A
2 1
0 0
Address 0x151B
2 1
PLL_MODE
0 1
for configuration details.
CS42L42
0
0
for details.
0
0
0
0
0
0
0
1
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