Cirrus Logic CS42L42 Manual page 144

7.6.14 Mixer Interrupt Mask
R/W
7
Default
0
Bits Name
7:4 —
3 M_EQ_BIQUAD_OVFL EQ_BIQUAD_OVFL mask.
2 M_EQ_OVFL
1 M_MIX_CHA_OVFL
0 M_MIX_CHB_OVFL
7.6.15 SRC Interrupt Mask
R/W
7
Default
0
Bits Name
7:4 — Reserved
3 M_SRC_ SRC_OUNLK mask.
OUNLK
0 Unmasked
1 (Default) Masked
2 M_SRC_ SRC_IUNLK mask.
IUNLK
0 Unmasked
1 (Default) Masked
1 M_SRC_OLK SRC_OLK mask.
0 Unmasked
1 (Default) Masked
0 M_SRC_ILK SRC_ILK mask.
0 Unmasked
1 (Default) Masked
7.6.16 ASP RX Interrupt Mask
R/W
7 6
—
Default 0 0
Bits Name
7:5 — Reserved
4 M_ASPRX_ ASPRX_OVFL mask.
OVLD
0 Unmasked
1 (Default) Masked
3 M_ASPRX_ ASPRX_ERROR mask.
ERROR
0 Unmasked
1 (Default) Masked
2 M_ASPRX_ ASPRX_LATE mask.
LATE
0 Unmasked
1 (Default) Masked
1 M_ASPRX_ ASPRX_EARLY mask.
EARLY
0 Unmasked
1 (Default) Masked
0 M_ASPRX_ ASPRX_NOLRCK mask.
NOLRCK
0 Unmasked
1 (Default) Masked
DS1083F2
6 5
—
0 0
Reserved
0 Unmasked
1 (Default) Masked
EQ_OVFL mask.
0 Unmasked
1 (Default) Masked
MIXER_CHx_OVFL mask.
0 Unmasked
1 (Default) Masked
6 5
—
0 0
5 4
M_ASPRX_OVLD M_ASPRX_ERROR M_ASPRX_LATE M_ASPRX_EARLY M_ASPRX_NOLRCK
0 1
4 3
M_EQ_
M_EQ_OVFL M_MIX_CHA_OVFL M_MIX_CHB_OVFL
BIQUAD_OVFL
0 1
Description
4 3
M_SRC_OUNLK M_SRC_IUNLK
0 1
Description
3
1
Description
7.6 Interrupt Registers
2 1
1 1
2 1
M_SRC_OLK
1 1
2 1
1 1
CS42L42
Address 0x1317
0
1
Address 0x1318
0
M_SRC_ILK
1
Address 0x1319
0
1
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