Interrupts - Cirrus Logic CS42L42 Manual

Table 4-30 describes the effects of resets on register fields. The SoundWire Slave IP supports asynchronous resets,
whose effects are described in
Registers
SCP/DPn interrupt mask (Sections 7.1.2, 7.1.14, 7.1.16, and 7.2.2)
CURRENT_BANK in the SCP control register
SCP device number (Section
Memory access status (Section
Memory read last address 0 and 1
INVERT_BANK bit in DPn Port control registers
DPn channel prepare status (Section
DPn channel enable (Section
SCP/DPn/general interrupt status
Section 7.1.13, Section 7.1.15)
All other SoundWire registers (address range below 0x1000)
Non-SoundWire registers (address range 0x1000 and above)
1.Bus reset, setting FORCE_RESET

4.18 Interrupts

The following sections describe the CS42L42 interrupt implementation.
4.18.1 SoundWire Interrupts
The SoundWire interrupt mechanism allows SoundWire slaves to alert the SoundWire master to abnormal events or error
conditions. SoundWire interrupts are implemented as defined by the SoundWire Specification. Their statuses are
combined into an interrupt status reported on the SoundWire bus, through the SoundWire General Interrupt Status 1
register; see Section 7.1.13). If this register indicates the presence of an interrupt condition, software must examine the
standard interrupts to determine the source.
Table 4-31 lists the SoundWire interrupts and corresponding mask registers. Note that, unlike other interrupts
implemented on the CS42L42, SoundWire interrupt mask bits are masked if cleared, rather than if set.
Table 4-31. SoundWire Interrupt Status Registers and Corresponding Mask Registers—Page 0x00
Section
Section 7.1, "SoundWire Control Port 0
Section 7.2, "SoundWire Data Port (1–3)
4.18.2 Standard Interrupts
The interrupt output pin, INT, is used to signal the occurrence of events within the device's interrupt status registers. Events
can be masked individually by setting corresponding bits in the interrupt mask registers.
and mask registers. The configuration of mask bits determines which events cause the immediate assertion of INT:
• When an unmasked interrupt status event is detected, the status bit is set and INT is asserted.
• When a masked interrupt status event is detected, the interrupt status bit is set, but INT is not affected.
Once asserted, INT remains asserted until all status bits that are unmasked and set have been read. Interrupt status bits
are sticky and read-to-clear: Once set, they remain set until the register is read and the associated interrupt condition is
not present. If a condition is still present and the status bit is read, although INT is deasserted, the status bit remains set.
To clear status bits set due to initiation of a path or block, the status bits must be read after the corresponding module is
enabled and before normal operation begins. Otherwise, unmasking previously set status bits causes assertion of INT.
DS1083F2
Table 4-30.
Table 4-30. Register Resets
(Section 7.1.3)
7.1.5)
7.1.17)
(Section 7.1.20)
(Section 7.2.3)
7.2.5)
7.2.7)
(Section 7.1.1, Section 7.2.1,
bit, or on exit from Clock Stop Mode if
Interrupt Source Status Register
Registers" SCP Interrupt Status 1 (Section
General Interrupt Status 1 (Section
Descriptions" DPn Interrupt Status (Section
POR/Device SoundWire
SoundWire Synchronization Loss Reset
Hard Reset Hard Reset 1
Reset to Reset to Reset to default
default default
Reset to Reset to Not reset
default default
Reset to Not reset Not reset
default
Reset to Reset to Not reset
default default
CLOCK_STOP_MODE is set. See
Name
7.1.1)
7.1.13)
7.2.1)
CS42L42
4.18 Interrupts
Table 4-29.
Interrupt Mask Register
SCP Interrupt Mask 1 (Section
General Interrupt Mask 1 (Section
DPn Interrupt Mask (Section 7.2.2)
Table 4-32 lists interrupt status
7.1.2)
7.1.14)
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