Cirrus Logic CS42L42 Manual page 143

7.6.10 VP Monitor Interrupt Status
R/O
7
Default
0
Bits Name
7:1 — Reserved
0 VPMON_TRIP VP monitor interrupt. If the VP power supply falls below 2.6 V, this bit is set. See
0 No interrupt
1 Interrupt detected
7.6.11 PLL Lock Interrupt Status
R/O
7
Default
0
Bits Name
7:1 — Reserved
0 PLL_LOCK PLL lock. Indicates the lock state of the PLL.
0 No interrupt
1 Interrupt detected
7.6.12 Tip/Ring Sense Plug/Unplug Interrupt Status
R/O
7
Default 0
Bits Name
7:4 — Reserved
3 TS_UNPLUG Tip sense unplug status. See
0 Condition is not present.
1 Condition is present.
2 TS_PLUG Tip sense plug status. See
0 Condition is not present.
1 Condition is present.
1 RS_UNPLUG Ring sense unplug status. See
0 Condition is not present.
1 Condition is present.
0 RS_PLUG Ring sense plug status. See
0 Condition is not present.
1 Condition is present.
7.6.13 ADC Overflow Interrupt Mask
R/W
7
Default
0
Bits Name
7:1 — Reserved
0 M_ADC_ ADC_OVFL mask.
OVFL
0 Unmasked
1 (Default) Masked
DS1083F2
6 5
0 0
6 5
0 0
6 5
—
0 0
Section 4.14.4
Section 4.14.4
Section 4.14.4
Section 4.14.4
6 5
0 0
4 3
—
0 0
Description
4 3
—
0 0
Description
4 3
TS_UNPLUG
0 x
Description
for details. Setting TS_INV reverses the meaning of this bit.
for details. Setting TS_INV reverses the meaning of this bit.
for details. Setting RS_INV reverses the meaning of this bit.
for details. Setting RS_INV reverses the meaning of this bit.
4 3
—
0 0
Description
7.6 Interrupt Registers
Address 0x130D
2 1
0 0
Section 4.15.1 for details.
Address 0x130E
2 1
0 0
Address 0x130F
2 1
TS_PLUG RS_UNPLUG
x x
Address 0x1316
2 1
0 0
CS42L42
0
VPMON_TRIP
x
0
PLL_LOCK
x
0
RS_PLUG
x
0
M_ADC_OVFL
1
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