Cirrus Logic CS42L42 Manual page 28

Table 3-25. Digital Interface Specifications and Characteristics
Test conditions (unless specified otherwise):
parameters can vary with VL and VP; min/max performance data taken with VCP = VA = 1.8 V, VD_FILT = 1.2 V; VP = 3.0–5.25 V; VL = 1.66–1.94 V
(VL_SEL = VP) or VL = 1.1–1.3 V (VL_SEL = GNDD); T
Input leakage current 2,3
Input leakage current (SoundWire)
ASP_SCLK/SWIRE_CLK and SWIRE_SD/ASP_SDIN only
Internal weak pull-down
Input capacitance 2
INT or WAKE current sink (V
OL
2
VL Logic (non-I C, including
SPDIF_TX)
VL Logic (I 2 C only)
VP Logic (excluding TIP_SENSE)
TIP_SENSE 5
RING_SENSE 6
RING_SENSE pull-up resistance
TIP_SENSE current to –VCP_FILT
RING_SENSE current to GND
1.See Table 1-1 for serial and control-port power rails.
2.Specification is per pin. The CS42L42 is not a low-leakage device, per the MIPI Specification. See
3.Includes current through internal pull-up or pull-down resistors on pin.
4.If VL = 0 V, the current must not exceed the values provided in
5.TIP_SENSE input circuit. This circuit allows the TIP_SENSE signal to go as low as –VCP_
FILT and as high as VP. Section 4.14.2
6.RING_SENSE input
circuit. This circuit
allows the RING_
SENSE signal to
RING_SENSE
range between
Pull - Up Resistance
–VCP_FILT and VP.
DS1083F2
Fig. 2-1 shows CS42L42 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground;
= +25°C; C
A
Parameters 1
ASP_SCLK/SWIRE_CLK, SWIRE_SD/ASP_SDIN
2 , 3
= 0.3 V maximum)
High-level output voltage (I
RS_TRIM_T
RS_TRIM_T = 1, High-level input voltage
RING_SENSE_PU_HIZ
RING_SENSE_PU_HIZ = 0; R
5
TIP_SENSE_CTRL
6
provides configuration details.
VP
ESD Protection
RING_SENSE
–VCP_FILT
= 60 pF.
L
ASP_SDOUT, ASP_LRCK/FSYNC
RING_SENSE, TIP_SENSE
INT, WAKE, RESET
Supplies as stipulated above
VD_FILT = 0 V (VL is as stated above)
= –100 µA)
OH
Low-level output voltage
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
Hysteresis voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
= 0, High-level input voltage
Low-level input voltage
Low-level input voltage
= 1, RS_TRIM_R = 0; R
PU
= 11 (Short-Detect Mode)
RS_TRIM_R = 0 (Hi-Z Mode)
Table 3-3.
–VCP_FILT
RING_SENSE
Current to GND
R R
PU-HIZ PU-MIDZ
To Digital
Input Circuitry
RING_SENSE
3 Characteristics and Specifications
Symbol Min
I —
in
—
—
SDA, SCL —
—
I —
in
—
VL = 0 V —
— 550
— —
— 825
V 0.9*VL
OH
V —
OL
V 0.7*VL
IH
V —
IL
V —
OL
V 0.7*VL
IH
V —
IL
V 0.05*VL
HYS
V —
OL
V 0.9
IH
V —
IL
V 0.87*VP
IH
V —
IL
V 0.15*VP
IH
V —
IL
V 0.40*VP
IH
V —
IL
to Hi-Z R -Hi-Z 1.688
PU PU
to Mid-Z R -MIDZ 12.15
PU
I 1.00
TIP_SENSE
I 1.00
RING_SENSE
Section 13.
ESD Protection
TIP_SENSE
Current to
–VCP_FILT
I
TIP_SENSE
TIP_SENSE
–VCP_FILT
VP
ESD Protection
R
PU-HIZ
I
RING_SENSE
–VCP_FILT
CS42L42
Max Unit
±4 µA
±3 µA
±100 nA
±100 nA
±100 nA
±3 µA
±3 µA
[4] mA
2450 k
10 pF
— µA
— V
0.1*VL V
— V
0.3*VL V
0.2*VL V
— V
0.3*VL V
— V
0.2 V
— V
0.2 V
— V
2.0 V
— V
0.03*VP V
— V
0.28*VP V
2.813 M
20.25 k
2.91 µA
3.2 µA
VP
To Digital
Input Circuitry
R
PU-MIDZ
To Digital
Input Circuitry
28