Cirrus Logic CS42L42 Manual page 72

The ASP_STP setting (see
• If ASP_STP = 0, the frame begins when LRCK/FSYNC transitions from high to low. See
x_STP = 0
LRCK
SCLK
Channel location index
x_CHy_LOC, x_CHz_LOC)
Previous Sample
SDIN/SDOUT
Previous Sample
This diagram assumes x_FSD = 0
• If ASP_STP = 1, the frame begins when LRCK/FSYNC transitions from low to high. See
LRCK
x_STP = 1
SCLK
Channel location index (x_CHy_LOC, x_CHz_LOC)
Previous Sample
SDIN/SDOUT
Previous Sample
In 50/50 Mode, left and right channels are programmed independently to output when LRCK/FSYNC is high or low—that
is, the channel-active phase. The active phase is controlled by the
AP (see Section 7.22). If x_AP = 1, the respective channel is output if LRCK/FSYNC is high. If x_AP = 0, the channel is
output if LRCK/FSYNC is low.
Note: Active phase has no function if 50/50 Mode = 0, ASP_RX0_2FS = 1, or ASP_RX1_2FS = 1.
In 50/50 Mode, the channel location (see
in a frame, the location of the last bit of each active phase is equal to (N/2) – 1.
4.9.6 Serial Port Status
Each serial port has sticky, write-1-to-clear status bits related to capture and render paths. These bits are described in
Section 7.6.4 and Section
a status bit is set. Table 4-18
If only one data-path direction (render/Tx or capture/Rx) of a serial port is used, the status bits of the unused direction may
be set. To prevent spurious interrupts, mask the status bits of unused data path directions and of unused serial ports.
Name Direction
Request Rx Set when too many input buffers request processing at the same time. If all channel
Overload registers are properly configured, this error status should never be set.
LRCK Error Rx Logical OR of LRCK Early and LRCK Late (see below).
DS1083F2
p. 138) determines which LRCK/FSYNC phase starts a frame in 50/50 Mode, as follows:
...
...
0 1 2
Channel y
x_CHy_LOC = 0, x_CHy_AP = 0
Channel z
x_CHz_LOC = 0, x_CHz_AP = 0
Figure 4-37. Example 50/50 Mode (ASP_STP = 0)
0 1 2
Channel y
x_CHy_LOC = 0, x_CHy_AP = 1
Channel z
x_CHz_LOC = 0, x_CHz_AP = 1
Figure 4-38. Example 50/50 Mode (ASP_STP = 1)
Section 4.9.3) is calculated within the channel-active phase. If there are N bits
7.6.5. Mask bits (Section 7.6.16
provides an overview.
Table 4-18. Serial Port Status
... 0
N/2 – 3 N/2 – 2 N/2 – 1
x_CHz_LOC = 0, x_CHz_AP = 1
x_CHy_LOC = 0, x_CHy_AP = 1
...
...
... 0
N/2 – 3 N/2 – 2 N/2 – 1
x_CHz_LOC = 0, x_CHz_AP = 0
x_CHy_LOC = 0, x_CHy_AP = 0
ASP_TX_CHx_AP
and Section 7.6.17) determine whether INT is asserted when
Description
4.9 Audio Serial Port (ASP)
Fig. 4-37.
...
...
1 2 ...
N/2 – 3 N/2 – 2 N/2 – 1
Channel z
Channel y
Fig. 4-38.
...
...
1 2 ...
N/2 – 3 N/2 – 2
Channel z
Channel y
(see p. 163) and ASP_RXx_CHy_
Register Reference
ASPRX_OVLD p. 140
ASPRX_ERROR p. 140
CS42L42
Next Sample
Next Sample
N/2 – 1
Next Sample
Next Sample
72