Id Registers - Cirrus Logic CS42L42 Manual

7.22.17 ASP Receive DAI1 Channel 2 Phase and Resolution
R/W
7
— ASP_RX1_CH2_AP
Default
0
Bits Name
7 — Reserved
6 ASP_ ASP receive DAI1 active phase. Valid only in 50/50 Mode (ASP_5050 = 1 and ASP_RXx_2FS = 0).
RX1_
0 (Default) Low. In 50/50 Mode, channel data is input when LRCK/FSYNC is low.
CH2_AP
1 High. In 50/50 Mode, channel data is input when LRCK/FSYNC is high.
5:2 — Reserved
1:0 ASP_ ASP receive DAI1 channel bit width. Sets the output resolution of the ASP receive DAI1 Channel x samples.
RX1_ 00 8 bits per sample (valid only for isochronous NFS and native mode)
01 16 bits per sample
CH2_RES
7.22.18 ASP Receive DAI1 Channel 2 Bit Start MSB
R/W
7
Default
0
Bits Name
7:1 — Reserved
0 ASP_RX1_CH2_ ASP receive DAI1 Channel 2 bit start MSB. Configures the MSB location of the channel with respect to SOF (LRCK
BIT_ST_MSB edge + phase lag)
7.22.19 ASP Receive DAI1 Channel 2 Bit Start LSB
R/O
7
Default 0
Bits Name
7:0 ASP_RX1_CH2_ ASP receive DAI1 Channel 2 bit start LSB. Configures the LSB location of the channel with respect to SOF (LRCK
BIT_ST_LSB edge + phase lag)

7.23 ID Registers

7.23.1 Subrevision
R/O
7
Default x
Bits Name
7:0 Subrevision. Identifies the CS42L42 subrevision. The Page 0x30 read sequence in
SUBREVISION
this register.
0000 0011 Initial version.
DS1083F2
6 5
0 0
6 5 4
—
0 0 0
6 5
0 0
6 5
x x
4 3
—
0 0
Description
3 2
0 0
Description
4 3
ASP_RX1_CH2_BIT_ST_LSB
0 0
Description
4 3
SUBREVISION
x x
Description
7.23 ID Registers
Address 0x2A11
2 1
ASP_RX1_CH2_RES
0 1
10 24 bits per sample
11 (Default) 32 bits per sample
Address 0x2A12
1
ASP_RX1_CH2_BIT_ST_MSB
0
2 1
0 0
2 1
x x
Section 5.4 must be followed to read
CS42L42
0
1
0
0
Address 0x2A13
0
0
Address 0x3014
0
x
168