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4 In/4 Out Audio CODEC with PCM and TDM Interfaces
DAC Features
Advanced multibit delta-sigma modulator
24-bit resolution
Differential or single-ended outputs
Dynamic range (A-weighted)
–
-109 dB differential
–
-105 dB single-ended
THD+N
–
-90 dB differential
–
-88 dB single ended
2 Vrms full-scale output into 3-k AC load
Rail-to-rail operation
ADC Features
Advanced multibit delta-sigma modulator
24-bit resolution
Differential inputs
-105 dB dynamic range (A-weighted)
-88 dB THD+N
2 Vrms full-scale input
AIN1 (±)
AIN2 (±)
AIN3 (±)
Multi-bit
AIN4 (±)
ADC
Digital Filters
SDOUT1
VL
1.8 to 5.0 VDC
Preliminary Product Information
http://www.cirrus.com
VDREG
2.5 V
Channel Volume ,
Mute, Invert ,
Noise Gate
Serial Audio Interface
Frame Sync
SDOUT2
SDIN2
SDIN1
Clock / LRCK
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2011
System Features
TDM, left justified, and I²S serial inputs and outputs
TM
I²C
host control port
Supports logic levels between 5 and 1.8 V
Supports sample rates up to 96 kHz
Common Applications
Automotive audio systems
AV, Blu-Ray, and DVD receivers
Audio interfaces, mixing consoles, and effects
processors
General Description
The CS4244 provides four multibit analog-to-digital and
four multi-bit digital-to-analog - converters and is
compatible with differential inputs and either differential
or single-ended outputs. Digital volume control, noise
gating, and muting is provided for each DAC path. A se-
lectable high-pass filter is provided for the 4 ADC inputs.
The CS4244 supports master and slave modes and
TDM, left-justified, and I²S modes.
This product is available in a 40-pin QFN package in
Automotive (-40 °C to +105 °C) and Commercial
(-40 °C to +85 °C) temperature grades. The CDB4244
Customer Demonstration Board is also available for de-
vice evaluation and implementation suggestions. See
"Ordering Information" on page 64
VA
5.0 VDC
LDO
Analog Supply
Master
Volume
Interpolation
Control
Filter
Level Translator
Serial Clock
Master Clock In
In/Out
(All Rights Reserved)
CS4244
for complete details.
DAC &
Multi-bit
Analog
Modulators
Filters
Control Port
2
INT
I
C Control
RST
Data
AOUT1 (±)
AOUT2 (±)
AOUT3 (±)
AOUT4 (±)
MAY '11
DS900PP2
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Related Manuals for Cirrus Logic CDB4244
Summary of Contents for Cirrus Logic CDB4244
- Page 1 In/Out Data 1.8 to 5.0 VDC This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2011 MAY ‘11 (All Rights Reserved) DS900PP2...
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Page 2: Table Of Contents
CS4244 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ..........................5 1.1 I/O Pin Characteristics ........................6 2. TYPICAL CONNECTION DIAGRAM ....................7 3. CHARACTERISTICS AND SPECIFICATIONS ..................8 RECOMMENDED OPERATING CONDITIONS ..................8 ABSOLUTE MAXIMUM RATINGS ......................8 DC ELECTRICAL CHARACTERISTICS ....................9 TYPICAL CURRENT CONSUMPTION .................... - Page 3 CS4244 LIST OF FIGURES Figure 1. CS4244 Pinout ..........................5 Figure 2. Typical Connection Diagram ......................7 Figure 3. Test Circuit for ADC Performance Testing ................. 13 Figure 4. PSRR Test Configuration ......................13 Figure 5. Equivalent Output Test Load ..................... 16 Figure 6.
- Page 4 CS4244 LIST OF TABLES Table 1. Speed Modes ..........................26 Table 2. Common Clock Frequencies ....................... 26 Table 3. Master Mode Left Justified and I²S Clock Ratios ................ 27 Table 4. Slave Mode Left Justified and I²S Clock Ratios ................27 Table 5.
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Page 5: Pin Descriptions
CS4244 1. PIN DESCRIPTIONS AOUT2+ SDIN1 AOUT2- AOUT3+ SDIN2 FS/LRCK AOUT3- Top-Down MCLK AOUT4+ (Though Package) SCLK AOUT4- View SDOUT1 VBIAS VREF VDREG Figure 1. CS4244 Pinout Pin Name Pin # Pin Description Serial Control Data (Input/Output) - Bi-directional data I/O for the I²C control port. SDINx Serial Data Input (Input) - Input channels serial audio data. -
Page 6: I/O Pin Characteristics
CS4244 Analog Power (Input) - Positive power for the analog sections. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VREF Analog Power Reference (Input) - Return pin for the VBIAS cap. VBIAS Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs. Negative Analog Output (Output) - Negative output signals from the internal digital to analog con- 25,27,29, Analog Output Characteristics... -
Page 7: Typical Connection Diagram
CS4244 2. TYPICAL CONNECTION DIAGRAM Rp (x4) **** Digital Signal Processor Pull Up or Down Based upon Desired Analog Output Filter * Address AOUT2+ Analog Output Filter * SDIN 1 AOUT2- SDIN 2 AOUT3+ Analog Output Filter * FS/LRCK AOUT3- MCLK AOUT4+ CS4244... -
Page 8: Characteristics And Specifications
CS4244 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 3) Parameters Symbol Units DC Power Supply 3.135 3.465 Analog Core 4.75 5.25 Level Translator 1.71 5.25 Temperature C Ambient Operating Temperature - Power Applied Automotive +105 C... -
Page 9: Dc Electrical Characteristics
CS4244 DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to ground. Parameters Units (Note 7) VDREG Nominal Voltage Output Impedance FILT+ Nominal Voltage Output Impedance k A DC Current Source/Sink Nominal Voltage 0.5•VA Output Impedance k A DC Current Source/Sink Notes:... -
Page 10: Typical Current Consumption
CS4244 TYPICAL CURRENT CONSUMPTION This table represents the power consumption for individual circuit blocks within the CS4244. CS4244 is configured as shown in Figure 2 on page VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC; F = 100 kHz;... -
Page 11: Analog Input Characteristics (Commercial Grade)
CS4244 ANALOG INPUT CHARACTERISTICS (COMMERCIAL GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. Input sine = 25 C; Measurement Bandwidth is 20 Hz to wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T 20 kHz unless otherwise specified;... -
Page 12: Analog Input Characteristics (Automotive Grade)
CS4244 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. Input sine = -40 to +105 C; Measurement Bandwidth is wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T 20 Hz to 20 kHz unless otherwise specified;... -
Page 13: Figure 3. Test Circuit For Adc Performance Testing
CS4244 634 470 pF 90.9 CS4244 AINx + 4.7 uF 100 k Analog Signal + 100 k 100 k 2700 pF 100 k 100 k Analog Signal - 100 k CS4244 AINx - 4.7 uF 90.9 470 pF 634 ... -
Page 14: Adc Digital Filter Characteristics
CS4244 ADC DIGITAL FILTER CHARACTERISTICS Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 7. Input sine = -40 to +105 C; Measurement Bandwidth is wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T 20 Hz to 20 kHz unless otherwise specified. -
Page 15: Analog Output Characteristics (Commercial Grade)
CS4244 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL GRADE) Test Conditions (unless otherwise specified). Device configured as shown in Section 2. on page VA_SEL = 0 for = 25 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz; Mea- VA = 3.3 VDC, 1 for VA = 5.0 VDC.; T surement Bandwidth is 20 Hz to 20 kHz;... -
Page 16: Analog Output Characteristics (Automotive Grade)
CS4244 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page VA_SEL = 0 for = -40 to +105 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz; VA = 3.3 VDC, 1 for VA = 5.0 VDC.;... -
Page 17: Combined Dac Interpolation & On-Chip Analog Filter Response
CS4244 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Test Conditions (unless otherwise specified): VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. The filter charac- teristics have been normalized to the sample rate (F ) and can be referenced to the desired sample rate by multi- plying the given characteristic by F Parameter... -
Page 18: Digital I/O Characteristics
CS4244 DIGITAL I/O CHARACTERISTICS Parameters Symbol Units High-Level Input Voltage (all input pins except (% of VL) (VL = 1.8 V) High-Level Input Voltage (all input pins except (% of VL) (VL = 2.5 V, 3.3 V, or 5 V) Low-Level Input Voltage (all input pins except (% of VL) High-Level Input Voltage (... -
Page 19: Switching Characteristics - Serial Audio Interface
CS4244 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. Parameters Symbol Units pin Low Pulse Width (Note 26) MCLK Frequency 7.68 25.6 (Note 27) MCLK Duty Cycle SCLK Duty Cycle Input Sample Rate (FS/LRCK pin) Single-Speed Mode Double-Speed Mode... -
Page 20: Figure 6. Tdm Serial Audio Interface Timing
CS4244 FS/LRCK (input) lcks SCLK (input) SDINx MSB-1 (input) SDOUT1 MSB-1 (output) Figure 6. TDM Serial Audio Interface Timing FS/LRCK (input/output) lcks SCLK (input/output) SDINx MSB-1 (input) SDOUTx MSB-1 (output) Figure 7. PCM Serial Audio Interface Timing DS900PP2... -
Page 21: Switching Specifications - Control Port
CS4244 SWITCHING SPECIFICATIONS - CONTROL PORT Test conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA load capacitance equal to maxi- mum value of C specified below (Note 31). Parameters Symbol Unit SCL Clock Frequency RESET Rising Edge to Start (Note 32) -
Page 22: Applications
CS4244 4. APPLICATIONS Power Supply Decoupling, Grounding, and PCB Layout As with any high-resolution converter, the CS4244 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 2 shows the recommended power ar- rangements, with VA connected to clean supplies. -
Page 23: Figure 9. System Level Initialization And Power-Up/Down Sequence
CS4244 4.2.2 Power-down To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn- ing off the power. In order to do this in a controlled manner, it is recommended that all the converters be muted to start the sequence. Next, set PDNx for all converters to 1 to power them down internally. Then, FS/LRCK and SCLK can be removed if desired. -
Page 24: I²C Control Port
CS4244 and 16, the VQ voltage will never rise to its minimum operating voltage. If the VQ voltage never rises above this minimum operating voltage, the device will not finish the power-up sequence and normal op- eration will not begin. Also note that any AOUTx±... -
Page 25: Figure 11. Timing, I²C Write
CS4244 The signal timings for a read and write cycle are shown in Figure 11 Figure 12. A Start condition is de- fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. -
Page 26: System Clocking
CS4244 4.3.1 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 4.3.1.1 Map Increment (INCR) The CS4244 has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to ‘0’, MAP will stay constant for successive I²C reads or writes. -
Page 27: Figure 13. Master Mode Clocking
CS4244 4.4.2 Master Mode Clock Ratios As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK is equal to F and SCLK is equal to 64x F as shown in Figure 13. TDM format is not supported in Master Mode. -
Page 28: Serial Port Interface
CS4244 Serial Port Interface The serial port interface format is selected by the Serial Port Format register bits. The TDM format is avail- able in Slave Mode only. 4.5.1 TDM Mode The serial port of the CS4244 supports the TDM interface format with varying bit depths from 16 to 24 as shown in Figure 15. -
Page 29: Figure 16. Serial Data Coding And Extraction Options Within The Tdm Streams
CS4244 DS900PP2... -
Page 30: Figure 17. Left Justified Format
CS4244 4.5.2 Left Justified and I²S Modes The serial port of the CS4244 supports the Left Justified and I²S interface formats with valid bit depths of 16, 18, 20, or 24 bits for the SDOUTx pins and 24 bits for the SDINx pins. All data is valid on the rising edge of SCLK. -
Page 31: Internal Signal Path
CS4244 Internal Signal Path 2.5 VDC 5.0 VDC 2.5 V Analog Supply AIN1 (±) AIN2 (±) AIN3 (±) Multi-bit AIN4 (±) ADC AOUT1 (±) Master AOUT2 (±) Volume Channel Volume , DAC & AOUT3 (±) Multi-bit Control Interpolation Mute, Invert , Analog AOUT4 (±) -
Page 32: Figure 20. Conventional Sdout (Left) Vs. Sidechain Sdout (Right) Configuration
CS4244 Device D Device D SDOUT1 SDOUT1 The ADC data of Device D is coded into the first four slots of the output TDM stream, Each of the device’s ADC data followed by the first 12 slots of the TDM is reflected in the TDM stream stream coming in on SDIN2, placing the SDIN2... - Page 33 CS4244 DS900PP2...
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Page 34: Figure 22. Example Serial Data Source Selection
CS4244 DS900PP2... -
Page 35: Figure 23. Adc Path
CS4244 4.6.2 ADC Path 2.5 VDC 5.0 VDC 2.5 V Analog Supply AIN1 (±) AIN2 (±) AIN3 (±) Multi-bit AIN4 (±) ADC AOUT1 (±) Master AOUT2 (±) Volume Channel Volume , DAC & AOUT3 (±) Multi-bit Control Interpolation Mute, Invert, Analog AOUT4 (±) -
Page 36: Figure 24. Single-Ended To Differential Active Input Filter
CS4244 634 470 pF ADC1-4 * Place close to AINx pins 91 22 F AINx+ 634 634 2700 pF 100 k 470 pF 100 k 91 100 k AINx- 0.01 F 22 F 100 k Figure 24. -
Page 37: Figure 26. Dac1-4 Path
CS4244 4.6.3 DAC1-4 Path 2.5 VDC 5.0 VDC 2.5 V Analog Supply AIN1 (±) AIN2 (±) AIN3 (±) Multi-bit AIN4 (±) ADC AOUT1 (±) Master AOUT2 (±) Volume Channel Volume , DAC & AOUT3 (±) Multi-bit Interpolation Control Mute, Invert , Analog AOUT4 (±) -
Page 38: Figure 27. De-Emphasis Curve
CS4244 De-emphasis is only available in Single-speed Mode. Gain T1=50 µs T2 = 15 µs -10dB Frequency 3.183 kHz 10.61 kHz Figure 27. De-emphasis Curve 4.6.4 Analog Outputs The recommended differential passive output filter is shown below. The filter has a flat frequency re- sponse in the audio band while rejecting as much signal energy outside of the audio band as possible. -
Page 39: Figure 29. Volume Implementation For The Dac1-4 Path
CS4244 4.6.5 Volume Control The CS4244 includes a volume control for the DAC1-4 signal path. The implementation details for the vol- ume control and other associated peripheries for DAC1-4 is shown in Figure 29 below. Digital volume steps, adjustable noise gating, muting, and soft ramping are provided on each DAC channel. DAC1-4 Noise INV DACx Gate Threshold... -
Page 40: Figure 30. Soft Ramp Behavior
CS4244 resulting in audible zipper noise if the ramp rate is set too high. By instead adapting the soft-ramp rate to fit the envelope given by the incoming volume samples, the envelope lag time is limited and the zipper noise is avoided. In this mode the soft ramp algorithm linearly interpolates the volume between the volume changes. -
Page 41: Table 6. Soft Ramp Rates
CS4244 lower values will permit closer tracking of the envelope but may re-introduce zipper noise. The default val- ues of these registers are recommended as a starting point. It is possible to disable the volume envelope tracking and always produce a constant ramp rate. To accomplish this, set the MIN DELAY[2:0] DELAY[2:0] values to match the... -
Page 42: Reset Line
CS4244 DAC1-4 NG[2:0] Setting Channel is muted after “x” bits Upper 13 Bits (-72 dB) Upper 14 Bits (-78 dB) Upper 15 Bits (-82 dB) Upper 16 Bits (-90 dB) Upper 17 Bits (-94 dB) Upper 18 Bits (-102 dB) Upper 24 Bits (-138 dB) Noise Gate Disabled Table 7. -
Page 43: Error Reporting And Interrupt Behavior
CS4244 Error Reporting and Interrupt Behavior The CS4244 is equipped with a suite of error reporting and protection. The types of errors that are detected, the notification method for these errors, and the steps needed to clear the errors are detailed in Table It is important to note that the interrupt notification bits for all of the errors are triggered on the edge of the occurrence of the event. - Page 44 CS4244 4.8.2 Interrupt Line Operation As mentioned previously, the interrupt line of the CS4244 will be pulled low or high (depending on the set- tings of the “INT PIN[1:0]” bits in the "Interrupt Control" register) after an interrupt condition occurs, pro- vided that the event is not masked in the mask register.
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Page 45: Figure 31. Interrupt Behavior And Example Interrupt Service Routine
CS4244 USER: Mask bit(s) set to 0 Unmasked error occurs Status Register bit changes to ‘1’ and INT pin set to active level USER: Read Status Registers (see status bit(s) = ‘1’) Mask bit(s) of corresponding status bit(s) set to ‘1’... -
Page 46: Register Quick Reference
CS4244 5. REGISTER QUICK REFERENCE Default values are shown below the bit names Function (Read Only Bits are shown in Italics) DEV. ID A[3:0] DEV. ID B[3:0] Device ID A & B p 48 DEV. ID C[3:0] DEV. ID D[3:0] Device ID C &... - Page 47 CS4244 Function (Read Only Bits are shown in Italics) MUTE DELAY[1:0] MIN DELAY[2:0] MAX DELAY[2:0] Volume Mode p 55 MASTER VOLUME[7:0] Master Volume p 56 DAC1 VOLUME[7:0] DAC1 Volume p 56 DAC2 VOLUME[7:0] DAC2 Volume p 56 DAC3 VOLUME[7:0] DAC3 Volume p 56 DAC4 VOLUME[7:0]...
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Page 48: Register Descriptions
CS4244 6. REGISTER DESCRIPTIONS All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state. Default values are shaded. Device I.D. A & B (Address 01h) (Read Only) Device I.D. C & D (Address 02h) (Read Only) Device I.D. -
Page 49: Clock & Sp Select (Address 06H)
CS4244 Clock & SP Select (Address 06h) BASE RATE[1:0] SPEED MODE[1:0] MCLK RATE[2:0] Reserved 6.3.1 Base Rate Advisory Advises the CS4244 of the base rate of the incoming base rate. This allows for the de-emphasis filters to be adjusted appropriately. The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz base rates. -
Page 50: Sample Width Select (Address 07H)
CS4244 Sample Width Select (Address 07h) SDOUTx SW[1:0] INPUT SW[1:0] Reserved[1:0] Reserved[1:0] 6.4.1 Output Sample Width These bits set the width of the samples placed into the outgoing SDOUTx streams. OUTPUT SW Sample Width is: 16 bits 18 bits 20 bits 24 bits Note: Bits which are wider than the Output Sample Width setting above will be set to zero within the... -
Page 51: Serial Port Data Select (Address 09H)
CS4244 6.5.3 Serial Data Output Sidechain Setting this bit enables the SDOUT1 side chain feature. In this mode, the samples from multiple devices can be coded into one TDM stream. See Section 4.6.2 ADC Path for more details. SDO CHAIN Sidechain is: Disabled Enabled... -
Page 52: Adc Control 1 (Address 0Fh)
CS4244 ADC Control 1 (Address 0Fh) Reserved Reserved VA_SEL ENABLE HPF INV. ADC4 INV. ADC3 INV. ADC2 INV. ADC1 6.7.1 VA Select Scales internal operational voltages appropriately for VA level. Configuring this bit appropriately for the VA voltage level used in the application is imperative to ensure proper operation and performance of the device. -
Page 53: Dac Control 1 (Address 12H)
CS4244 DAC Control 1 (Address 12h) DAC1-4 NG DAC1-4 DE Reserved Reserved Reserved 6.9.1 DAC1-4 Noise Gate This sets the bit depth at which the Noise Gate feature should engage for the DAC1-4 path. DAC1-4 NG[2:0] Noise Gate is set at: [b] Upper 13 Bits (72 dB) Upper 14 Bits (78 dB) Upper 15 Bits (84 dB) -
Page 54: Dac Control 3 (Address 14H)
CS4244 6.11 DAC Control 3 (Address 14h) Reserved DAC1-4 ATT Reserved Reserved MUTE DAC4 MUTE DAC3 MUTE DAC2 MUTE DAC1 6.11.1 DAC1-4 Attenuation Sets the mode of attenuation used for the DAC1-4 path. DAC1-4 ATT Attenuation events happen: On a soft ramp Immediately Note: Please see... -
Page 55: Volume Mode (Address 16H)
CS4244 6.13 Volume Mode (Address 16h) MUTE DELAY[1:0] MIN DELAY[2:0] MAX DELAY[2:0] 6.13.1 Mute Delay Sets the delay between the volume steps during the muting and un-muting of a signal when the attenua- 6.02 tion mode is set to soft ramp. Each step of the ramp is equal to dB ~= 0.094 dB. -
Page 56: Master And Dac1-4 Volume Control (Address 17H, 18H, 19H, 1Ah, & 1Bh)
CS4244 6.14 Master and DAC1-4 Volume Control (Address 17h, 18h, 19h, 1Ah, & 1Bh) x VOLUME[7:0] 6.14.1 x Volume Control 6.02 Sets the level of the x Volume Control. Each volume step equals dB ~= 0.38 dB. See Section 4.6.5.1 on page 39 for the muting behavior of these volume registers. -
Page 57: Interrupt Mask 1 (Address 1Fh)
CS4244 6.16 Interrupt Mask 1 (Address 1Fh) MASK MASK MASK Reserved MASK MASK MASK MASK TST MODE ERR SP ERR CLK ERR ADC4 OVFL ADC3 OVFL ADC2 OVFL ADC1 OVFL 6.16.1 Test Mode Error Interrupt Mask Allows or prevents a Test Mode Error event from flagging the interrupt pin. A test mode error occurs when an inadvertent I²C write places the device in test mode. -
Page 58: Interrupt Mask 2 (Address 20H)
CS4244 6.17 Interrupt Mask 2 (Address 20h) MASK MASK MASK MASK Reserved Reserved Reserved Reserved DAC4 CLIP DAC3 CLIP DAC2 CLIP DAC1 CLIP 6.17.1 DACx Clip Interrupt Mask Allows or prevents a DACx Clip event from flagging the interrupt pin. MASK In the event of a DACx Clip event, Interrupt Pin will: DACx CLIP... -
Page 59: Interrupt Notification 2 (Address 22H) (Read Only)
CS4244 6.19 Interrupt Notification 2 (Address 22h) (Read Only) Reserved Reserved Reserved Reserved DAC4 CLIP DAC3 CLIP DAC2 CLIP DAC1 CLIP 6.19.1 DACx Clip A DACx Clip has occurred since the last clearing of the Interrupt Notification register. DACx CLIP Since the last clearing of the Interrupt Notification Register, a DACx Clip Error: Has Not Occurred Has Occurred... -
Page 60: Adc Filter Plots
CS4244 7. ADC FILTER PLOTS Stopband Rejection Transition Band −10 −10 −20 −20 −30 −30 −40 −40 −50 −50 −60 −60 −70 −70 −80 −80 −90 −90 −100 −100 0.42 0.44 0.46 0.48 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 32. -
Page 61: Dac Filter Plots
CS4244 8. DAC FILTER PLOTS Figure 38. SSM DAC Stopband Rejection Figure 39. SSM DAC Transition Band Figure 40. SSM DAC Transition Band (Detail) Figure 41. SSM DAC Passband Ripple DS900PP2... -
Page 62: Figure 42. Dsm Dac Stopband Rejection
CS4244 Figure 42. DSM DAC Stopband Rejection Figure 43. DSM DAC Transition Band Figure 44. DSM DAC Transition Band (Detail) Figure 45. DSM DAC Passband Ripple DS900PP2... -
Page 63: Package Dimensions
CS4244 9. PACKAGE DIMENSIONS 40L QFN (6 6 MM BODY) PACKAGE DRAWING 2.00 REF PIN #1 CORNER PIN #1 IDENTIFIER 0.500.10 LASER MARKING Figure 46. Package Drawing INCHES MILLIMETERS NOTE 0.0394 1.00 0.0000 0.0020 0.00 0.05 .0071 .0091 .0110 0.18 0.23 0.28... -
Page 64: 10.Ordering Information
Description Package Temp Range Container Pb-Free Grade Order# Rail CS4244-CNZ Commercial -40° to +85°C Tape and CS4244-CNZR Reel CS4244 4 In/4 Out CODEC 40-QFN Rail CS4244-ENZ Automotive -40° to +105°C Tape and CS4244-ENZR Reel CDB4244 CS4244 Evaluation Board CDB4244 DS900PP2... -
Page 65: 11.Revision History
CS4244 11.REVISION HISTORY Release Changes – Initial Release – Remove analog input single-ended mode from document. – Updated Internal Connections in Section 1.1 I/O Pin Characteristics. – Changed VA range in Recommended Operating Conditions table. – Updated group delay and HPF specifications in the ADC Digital Filter Characteristics table. - Page 66 TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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