Fractional-N Pll Registers - Cirrus Logic CS42L42 Manual

7.6.20 VP Monitor Interrupt Mask
R/W
7
Default
0
Bits Name
7:1 — Reserved
0 M_ VP monitor mask.
VPMON_
0 Unmasked. Unmask/enable this bit only when VP exceeds the detection voltage threshold; applicable to power-up
TRIP
conditions or if VP is not at its steady-state voltage.
1 (Default) Masked
7.6.21 PLL Lock Mask
R/W
7
Default 0
Bits Name
7:1 — Reserved
0 M_PLL_ PLL lock mask.
LOCK
0 Unmasked
1 (Default) Masked
7.6.22 Tip/Ring Sense Plug/Unplug Interrupt Mask
R/W
7
Default 0
Bits Name
7:4 — Reserved
3 M_TS_ Tip sense unplug mask.
UNPLUG
0 Unmasked
1 (Default) Masked
2 M_TS_ Tip sense plug mask.
PLUG
0 Unmasked
1 (Default) Masked
1:0 — Reserved
1 M_RS_ Ring sense unplug mask.
UNPLUG
0 Unmasked
1 (Default) Masked
0 M_RS_ Ring sense plug mask.
PLUG
0 Unmasked
1 (Default) Masked

7.7 Fractional-N PLL Registers

7.7.1 PLL Control 1
R/W
7
Default
0
Bits Name
7:1 — Reserved
0 PLL_ PLL start. If MCLK_SRC_SEL = 0, the PLL is bypassed and can be powered down by clearing PLL_START. See
START
0 (Default) Powered off.
1 Powered on
DS1083F2
6 5
0 0
6 5
0 0
6 5
—
0 0
6 5
0 0
4 3
—
0 0
Description
4 3
—
0 0
Description
4 3
M_TS_UNPLUG
0 1
Description
4 3
—
0 0
Description
7.7 Fractional-N PLL Registers
2 1
M_VPMON_TRIP
0 0
2 1
0 0
2 1
M_TS_PLUG M_RS_UNPLUG M_RS_PLUG
1 1
2 1
0 0
CS42L42
Address 0x131E
0
1
Address 0x131F
0
M_PLL_LOCK
1
Address 0x1320
0
1
Address 0x1501
0
PLL_START
0
Section 4.7.3.
146