Cirrus Logic CS42L42 Manual page 34

To avoid audible distortion when inputs to the equalizer are extremely large, the gain must be limited to 0 dB for each filter
stage and all B coefficients must be between ±1.0.
As Table 4-2 shows, coefficients are represented in binary by 32-bit signed values stored in S1.30 two's complement format.
The 2 MSBs represent the sign bit and whole-number portion of the decimal coefficient. The 30 LSBs represent the fractional
portion of the coefficient. Coefficients must be in the range of –2.00000 to 1.999999999 (0x8000 0000–0x7FFF FFFF).
Precision of Coefficients Order of Filter Sample Rate
S1.30
describes three-band equalizer registers. All coefficients are configured as pass-through at power-up.
Section 7.16
Note: Filters are read and written by using
accessed only as part of a full-filter access procedure; otherwise, the three-band filter may be corrupted and audio
artifacts may occur.
Use Ex. 4-1 to write EQ filter coefficients.
Example 4-1. Writing the EQ Filter Coefficients
S T
TEP ASK
1 Ensure EQ initialization is complete (EQ_
INIT_DONE = 1).
Note: polling EQ_INIT_DONE is valid only
if EQ PDN = 0 (EQ is powered up.)
2 Clear the equalizer start filter bit to allow
writing coefficients.
3 Disable the EQ bypass.
4 Mute the EQ input path.
5 Set the EQ write enable bit.
6 Write input coefficients. There are 15 32-bit coefficients and four 8-bit registers, so 60 register writes are required.
The biquad order is as follows: 1, 2, 3
The coefficient order is as follows: b0, b1, a1, a2, b2
The sequence shown in Steps 6.1 through 6.4 writes a single coefficient for a single biquad: This process is repeated 15 times.
The order of coefficients is as follows:
Biquad 1, b0
Biquad 1, b1
Biquad 1, a1
...
Biquad 3, b2
6.1 Write EQ_COEF_IN[7:0] (0x2401)
6.2 Write EQ_COEF_IN[15:8]
(0x2402)
6.3 Write EQ_COEF_IN[23:16]
(0x2403)
6.4 Write EQ_COEF_IN[31:24]
(0x2404, see note below)
DS1083F2
Table 4-2. Equalizer Filter Formatting (Fs
3 biquads Fs
INT
EQ_COEF_OUT
R
EGISTER
Equalizer Initialization Status
Reserved
EQ_INIT_DONE
R
EGISTER
Equalizer Start Filter Control
Reserved
EQ_START_FILTER
R
EGISTER
Serial Port SRC Control
Reserved
EQ_BYPASS
I2C_DRIVE
ASP_DRIVE
SRC_BYPASS_DAC
SRC_BYPASS_ADC
R
EGISTER
Equalizer Input Mute Control
Reserved
EQ_MUTE
R
EGISTER
Equalizer Filter Coefficient Read/Write
Reserved
EQ_WRITE
EQ_READ
R
EGISTER
Equalizer Filter Coefficient Input 0–3
EQ_COEF_IN[7:0]
Equalizer Filter Coefficient Input 0–3
EQ_COEF_IN[15:8]
Equalizer Filter Coefficient Input 0–3
EQ_COEF_IN[23:16]
Equalizer Filter Coefficient Input 0–3
EQ_COEF_IN[31:24]
= 48 kHz)
INT
Coefficient Design Base
–1
z (For z –1 , design the coefficients at the rate of the filter.)
and EQ_COEF_IN
/B F
IT IELDS
/B F
IT IELDS
/B F
IT IELDS
/B F
IT IELDS
/B F
IT IELDS
/B F
IT IELDS
4.3 Three-Band Equalizer
Length (in Bytes)
(see p. 156). However, they must be
V D
ALUE ESCRIPTION
0x01
0000 000
—
1
EQ initialization complete.
V D
ALUE ESCRIPTION
0x00
0000 000
—
0
Coefficients can be read or written
V D
ALUE ESCRIPTION
0x00
000
—
0
No bypass
0
Normal
0
Normal
0
No bypass
0
No bypass
V D
ALUE ESCRIPTION
0x01
0000 000
—
1
Mute EQ Channel input.
V D
ALUE ESCRIPTION
0x02
0000 00
—
1
Enable EQ write.
0
Disable EQ read.
V D
ALUE ESCRIPTION
0xXX
Coefficient write
0xXX
Coefficient write
0xXX
Coefficient write
0xXX
Coefficient write
CS42L42
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