Global Registers - Cirrus Logic CS42L42 Manual

Address
Function
+0x24 DPn Offset
Control 1
p. 126
+0x25 DPn Offset
Control 2
p. 126
+0x26 DPn Horizontal
Control
p. 126
+0x27 DPn Block Control 3
p. 127
+0x28–+0xFF Reserved

6.4 Global Registers

I 2 C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94(Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Address Function
0x00 Control Port Page
Device ID A and B
0x01
(Read Only)
p. 127
Device ID C and D
0x02
(Read Only)
p. 127
Device ID E and F
0x03
(Read Only)
p. 127
0x04 Reserved
Revision ID (Read
0x05
Only)
p. 127
Freeze Control
0x06
p. 128
Serial Port SRC
0x07
Control
p. 128
MCLK Status
0x08
(Read Only)
p. 128
MCLK Control
0x09
p. 129
Soft Ramp Rate
0x0A
p. 129
Slow Start Enable
0x0B
p. 129
0x0C–0x0D Reserved
I 2 C Debounce
0x0E
p. 130
I 2 C Stretch
0x0F
p. 130
2
I C Timeout
0x10
p. 130
0x11–0x7F Reserved
DS1083F2
Slave Data Port 1–3, 15 Registers
7 6
0 0
0 0
HSTART
0 0
0 0
Page 0x10—Global Registers
7 6
0 0
DEVIDA
0 1
DEVIDC
1 0
DEVIDE
0 0
x x
AREVID
x x
0 0
—
0 0
0 0
0 0
ASR_RATE
1 0
— SLOW_START_EN
0 1
x x
I2C_SDA_DBNC_CNT
1 0
0 0
MAS_I2C_ MAS_TO_DIS
NACK
1 0
x x
5 4 3
OFFSET1
R/W
0 0 0
OFFSET2
R/W
0 0 0
R/W
0 0 0
—
—
0 0 0
—
5 4 3
PAGE
0 1 0
0 0 0
1 0 0
1 0 x
—
x x x
x x x
—
0 0 0
EQ_BYPASS I2C_DRIVE
0 1 0
—
0 0 0
—
0 0 0
1 0 0
1 1 0
—
x x x
I2C_SDA_
DBNC_EN
0 0 1
I2C_STRETCH
0 0 0
MAS_TO_SEL ACC_TO_DIS
1 1 0
—
x x x
CS42L42
6.4 Global Registers
2 1
0 0
0 0
HSTOP
0 0
0 0
2 1
0 0
DEVIDB
0 1
DEVIDD
1 0
—
x x
x x
MTLREVID
x x
0 0
ASP_DRIVE SRC_
BYPASS_DAC
0 0
INTERNAL_
FS_STAT
0 x
INTERNAL_FS
0 1
DSR_RATE
1 0
—
0 0
x x
I2C_SCL_DBNC_CNT
0 0
0 1
ACC_TO_SEL
1 1
x x
0
0
0
0
BLOCK_
PACKING_
MODE
R/W
0
0
0
0
0
x
x
x
FREEZE
0
SRC_
BYPASS_ADC
0
—
0
—
0
0
0
x
I2C_SCL_
DBNC_EN
0
1
1
x
106