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6.6 Clocking Registers
I
2
C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Address
Function
0x00
Control Port Page
MCLK Source Select
0x01
p. 136
S/PDIF Clock
0x02
Configuration
p. 136
FSYNC Pulse Width
0x03
Lower Byte
p. 137
FSYNC Pulse Width
0x04
Upper Byte
p. 137
FSYNC Period Lower
0x05
Byte
p. 137
FSYNC Period Upper
0x06
Byte
p. 137
ASP Clock
0x07
Configuration 1
p. 138
ASP Frame
0x08
Configuration
p. 138
Fs Rate Enable
0x09
p. 138
Fs Rate Enable
0x09
p. 138
Input ASRC Clock
0x0A
Select
p. 139
Output ASRC Clock
0x0B
Select
p. 139
PLL Divide
0x0C
Configuration 1
p. 139
0x0D–0x7F Reserved
6.7 Interrupt Registers
I
2
C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read)
Address
Function
0x00
Control Port Page
ADC Overflow
0x01
Interrupt Status (Read
p. 139
Only)
Mixer Interrupt Status
0x02
(Read Only)
p. 139
SRC Interrupt Status
0x03
(Read Only)
p. 140
ASP RX Interrupt
0x04
Status (Read Only)
p. 140
0x05
ASP TX Interrupt
Status (Read Only)
p. 141
0x06–0x07 Reserved
Codec
Interrupt
0x08
Status (Read Only)
p. 141
DS1083F2
Page 0x12—Clocking Registers
7
6
5
0
0
0
0
0
0
—
0
0
0
0
0
0
—
0
0
0
1
1
1
—
0
0
0
—
ASP_SCLK_
EN
0
0
0
—
0
0
0
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
Page 0x13—Interrupt Registers
7
6
5
0
0
0
0
0
0
—
0
0
0
—
0
0
0
—
0
0
0
—
0
0
0
x
x
x
0
0
0
4
3
PAGE
1
0
—
0
0
SPDIF_CLK_DIV
SPDIF_LRCK_
0
0
FSYNC_PULSE_WIDTH_LB
0
0
0
0
FSYNC_PERIOD_LB
1
1
0
0
ASP_
ASP_SCPOL_
HYBRID_
IN_ADC
MODE
0
0
ASP_STP
ASP_5050
1
0
0
0
—
0
0
—
0
0
—
0
0
—
0
0
—
x
x
4
3
PAGE
1
0
—
0
0
EQ_BIQUAD_
OVFL
0
x
SRC_OUNLK
0
x
ASPRX_OVLD
ASPRX_
ERROR
x
x
ASPTX_
SMERROR
0
x
—
x
x
—
0
0
CS42L42
6.6 Clocking Registers
2
1
0
1
MCLKDIV
MCLK_SRC_
0
0
SPDIF_LRCK_
SRC_SEL
CPOL
0
0
0
0
FSYNC_PULSE_WIDTH_UB
0
0
0
0
FSYNC_PERIOD_UB
0
0
ASP_SCPOL_
ASP_LCPOL_
ASP_LCPOL_
IN_DAC
OUT
0
0
ASP_FSD
0
0
FS_EN
0
0
FS_EN
0
0
CLK_IASRC_SEL
0
0
CLK_OASRC_SEL
0
0
SCLK_PREDIV
0
0
x
x
2
1
0
1
ADC_OVFL
0
0
EQ_OVFL
MIX_CHA_
MIX_CHB_
OVFL
x
x
SRC_IUNLK
SRC_OLK
x
x
ASPRX_LATE
ASPRX_
EARLY
x
x
ASPTX_LATE
ASPTX_
EARLY
x
x
x
x
HSDET_
PDN_DONE
AUTO_DONE
0
x
0
0
SEL
0
—
0
0
0
1
0
IN
0
0
0
0
0
0
0
x
0
1
x
OVFL
x
SRC_ILK
x
ASPRX_
NOLRCK
x
ASPTX_
NOLRCK
x
x
x
108
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