Soundwire Interface - Cirrus Logic CS42L42 Manual

4.7.3.4 Powering Down the PLL
To power down the PLL, clear PLL_START.

4.8 SoundWire Interface

The MIPI-compliant SoundWire slave interface transports control and audio data. The external SoundWire master
interface communicates with the CS42L42 SoundWire slave using SWIRE_SD and SWIRE_CLK (described in
which are shared with all devices on the SoundWire bus. The interface is an alternative to the ASP and I
audio and control-data transfer. SoundWire allows connection of all compatible audio sources and audio sinks over a
single two-wire connection. The system includes the following features:
• Transporting payload, control, and setup data on a single two-wire interface
• Double data rate (DDR) transmission
• Direct slave-to-slave data transport
• Isochronous and asynchronous audio streams
• Asynchronous wake events can be generated as part of Clock Stop Mode
See the MIPI SoundWire Specification for details regarding features such as framing and synchronization.
4.8.1 Physical Interface and Data Encoding
The SoundWire interface has two logical signals:
• SWIRE_CLK—A system clock signal that is distributed from the master.
• SWIRE_SD—Data signal that can be driven by master or slave.
The interface uses conventional single-ended voltage-level signaling. The data encoding is modified NRZI, where an
unchanging physical value (i.e., an encoded logic zero) is not actively driven, but is maintained by a bus keeper within the
master. The bus keeper facilitates detection of undriven bit-symbol periods to identify errors and to handle systems that
are not fully populated.
DDR signaling halves the required frequency of the clock signal, which reduces overall system power consumption.
4.8.2 Frame Structure
A SoundWire bit stream is a continuous stream of bits encoded using the modified-NRZI scheme. The bit stream is divided
into a repetitive sequence of blocks of bits (i.e., frames). A frame consists of bit-symbol periods (i.e., bit slots) that
correspond to one-half cycle of the clock signal. Each frame is constructed as a two-dimensional array of these bit slots
made from 48 to 256 rows with 2 to 16 columns. The number of rows and columns is programmable. This provides a simple
way to identify periodic positions within the bit stream to multiplex data from multiple sources.
DS1083F2
CS42L42
4.8 SoundWire Interface
Table 1-1),
2 C interfaces for
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