System Applications; Power-Up Sequence - Cirrus Logic CS42L42 Manual

Group
Headset (see Section 7.6.7 and
Section 7.6.8
)
DAC and ADC (see Section 7.6.9
VP monitor (see Section 7.6.10
)
PLL (see Section 7.6.11
Tip sense and ring sense plug/unplug
)
status (see Section 7.6.12
1.Reading this bit following an early LRCK/SM error/no LRCK returns a 1. Subsequent reads return a 0. Valid LRCK transitions or exiting the transmit
overflow condition rearms the detection of the corresponding event. See

5 System Applications

This section provides recommended procedures and instruction sequences for standard operations.

5.1 Power-Up Sequence

Ex. 5-1 is the procedure for implementing HP playback from the ASP. This example sequence configures the CS42L42
for SCLK = 12.288 MHz, LRCK = 48 kHz, and TDM playback, in Slave Mode.
Example 5-1. Power-Up Sequence
S T
TEP ASK
1 Apply all relevant power supplies, then assert
2 Wait 2.5 ms.
3 Power up the codec.
4 Configure the device's ASP and ASP SRC.
4.1 Configure switch
from RCO to SCLK.
4.2 Power down the
RCO.
4.3 Configure device's
internal sample rate
with the applied
MCLK signal.
4.4 Select MCLK
source.
4.5 Configure the
FSYNC period.
4.6 Configure the
FSYNC period.
4.7 Configure FSYNC
pulse width.
DS1083F2
Table 4-33. Interrupt Source Types (Cont.)
HSBIAS_SENSE
TIP_SENSE_PLUG
TIP_SENSE_UNPLUG
DETECT_TRUE_FALSE
DETECT_FALSE_TRUE
SHORT_RELEASE
SHORT_DETECTED
)
DAC_LK
ADC_LK
)
VPMON_TRIP
PLL_LOCK
TS_UNPLUG
TS_PLUG
RS_UNPLUG
RS_PLUG
R /B F
EGISTER IT
before applying SCLK and LRCK to the CS42L42.
RST
Power Down Control 2. 0x1102
Reserved
DISCHARGE_FILT+
SRC_PDN_OVERRIDE
ASP_DAI1_PDN
DAC_SRC_PDNB
ADC_SRC_PDNB
Oscillator Switch Control. 0x1107
Reserved
SCLK_PRESENT
Oscillator Switch Status. 0x1109
Reserved
OSC_PDNB_STAT
OSC_SW_SEL_STAT
MCLK Control. 0x1009
Reserved
INTERNAL_FS
Reserved
MCLK Source Select. 0x1201
Reserved
MCLKDIV
MCLK_SRC_SEL
FSYNC Period, Lower Byte. 0x1205
FSYNC_PERIOD_LB
FSYNC Period, Upper Byte. 0x1206
FSYNC_PERIOD_UB
FSYNC Pulse Width, Lower Byte. 0x1203
FSYNC_PULSE_WIDTH_LB
Status Registers
Table 4-18 for details.
V
IELDS ALUE
0x83
100
0
0
0
1
1
0x01
0000 000
1
0x01
0000 0
0
01
0x02
0000 00
1
0
0x00
0000 00
0
0
0xFF
1111 1111 256 SCLKs per LRCK lower byte.
0x00
0000 0000 0 SCLKs per LRCK upper byte
0x1F
0001 1111 LRCK is one SCLK Wide.
5 System Applications
Interrupt Source Type
All are events.
Condition
Condition
Condition
Condition
Events.
Although a true event interrupt
clears when read, these dynamically reflect
the state of the debounced input signal.
D
ESCRIPTION
—
FILT+ is not clamped to ground.
SRC is powered up.
ASP is powered up.
DAC SRC is powered up.
ADC SRC is powered up.
—
SCLK is present.
—
RCO powered down
RCO selected for internal MCLK
—
Internal sample rate is MCLK/256= 48 kHz.
—
—
Divide by 1.
SCLK pin is MCLK source.
CS42L42
89