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Cirrus Logic CS42L42 Manual

Low-power audio codec with soundwire-i2s/tdm and audio processing
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Low-Power Audio Codec with SoundWire™–I
System Features
• Stereo headphone (HP) output with 114-dB dynamic range
— Class H HP amplifier with four-level automatic or
manual supply adjust
— Power output 2 x 35 mW into 30 
• Mono mic input with 114-dB dynamic range
— Low-noise headset bias with integrated bias resistor
— 1-V
input voltage
RMS
— Integrated AC-coupling capacitors
• Integrated detect features
— OMTP (Open Mobile Terminal Platform) and AHJ
(American headset jack) headset-type detection and
configuration with low-impedance internal switches
— Mic short (S0 Button) detect with ADC automute
— Automatic Hi-Z of headset bias output to ground on
headset bias current rise or HP/headset unplug
• System wake from headset/headphone plug/unplug or
S0 button press
• Interrupt output
• Mono equalizer for side-tone mix
®
• MIPI
SoundWire™ or I
interface
• S/PDIF transmit (Sony/Philips digital interface format)
MCLK
HSIN+
+
ADC
HSIN–
–
HS Bias LDO
HS4
HS3
Headset
HS_CLAMP1
Detect,
Switches,
HS_CLAMP2
and Depletion
HS4_REF
FET Control
HS3_REF
RING_SENSE
TIP_SENSE
Headphone Detect
INT
http://www.cirrus.com
2
C/I
2
S/TDM control and audio
VA
Analog
Core
Windnoise
Filter
HPF /
Decimators
Mute
MCLK
Clock
SRC
Gen
PLL
DAO
SWIRE_CLK/
ASP_SDOUT
WAKE
ASP_SCLK
Copyright  Cirrus Logic, Inc. 2014–2017
2
S/TDM and Audio Processing
• Integrated fractional-N PLL
— Increases system-clock flexibility for audio processing
— Reference clock sourced from either I
or MIPI SoundWire clock
• Audio serial port (ASP)
2
— I
S (two channels) or TDM (up to four channels)
— Slave or Hybrid-Master Mode (bit-clock slave and
LRCK/FSYNC derived from bit clock)
— Sample-rate converter (SRC) for two input channels,
with bypass
— SRC for one output channel, with bypass
— User isochronous audio transport support
— Supports up to 192-kHz sample rate to S/PDIF output
— Sample rate support for 8 to 192 kHz
• Integrated power management
— Digital core operates from either an external 1.2-V
supply or LDO from a 1.8-V supply.
— Step-down charge pump improves HP efficiency
— Independent peripheral power-down controls
— Standby operation from VP with all other supplies
powered off
— VP monitor to detect and report brownout conditions
— Low-impedance switching suppresses ground-noise
Applications
• Ultrabooks, tablets, and smartphones
• Digital headsets
DIGLDO_PDN
CS42L42
EQ
ADC
Downlink
Downlink
SRC
SRC
2
2
2
2
SoundWire
Audio and
DAI
Control
Port
SWIRE_SD/
ASP_LRCK/
SWIRE_SEL
ASP_SDIN
FSYNC
(All Rights Reserved)
CS42L42
VL VD_FILT
VP
LDO
with
POR
LDO
VP_CP
Bypass
Digital
Core
MCLK
Interpolator
Mute
DAC
Interpolator
Mute
DAC
Pseudodifferential Input
2
I
C Slave
AD0 AD1
SPDIF_TX
SDA
SCL
2
S/TDM bit clock
VCP
+VCP_FILT
Step -Down
–VCP_FILT
Inverting
HPSENSA
+VCP_FILT
–
HPOUTA
+
–
VCP_FILT
HPSENSB
+VCP_FILT
–
HPOUTB
+
–
VCP_FILT
S/PDIF
DS1083F2
AUG '17

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Summary of Contents for Cirrus Logic CS42L42

  • Page 1 FET Control HS3_REF RING_SENSE S/PDIF TIP_SENSE Headphone Detect SoundWire C Slave Audio and Control Port AD0 AD1 SPDIF_TX SWIRE_CLK/ ASP_SDOUT SWIRE_SD/ ASP_LRCK/ SWIRE_SEL WAKE ASP_SCLK ASP_SDIN FSYNC DS1083F2 Copyright  Cirrus Logic, Inc. 2014–2017 AUG ‘17 (All Rights Reserved) http://www.cirrus.com...

  • Page 2: Table Of Contents

    ADC for audio capture. The CS42L42 provides high performance (up to 24-bit) audio for ADC and DAC audio playback and capture functions as well as for the S/PDIF transmitter. The CS42L42 architecture includes bypassable SRCs and a bypassable, three-band, 32-bit parametric equalizer that allows processing of digital audio data.

  • Page 3: Pin Assignments And Descriptions

    CS42L42 1 Pin Assignments and Descriptions 1 Pin Assignments and Descriptions This section shows pin assignments and describes pin functions. 1.1 WLCSP Pin Out (Through-Package View) ASP_SDOUT ASP_SDIN/ SPDIF_TX VD_FILT SWIRE_SD GNDL ASP_SCLK/ ASP_LRCK/ GNDD SWIRE_CLK FSYNC FILT+ GNDA VL_SEL...

  • Page 4: Qfn Pin Out (Through-Package View)

    CS42L42 1.2 QFN Pin Out (Through-Package View) 1.2 QFN Pin Out (Through-Package View) RESET WAKE DIGLDO_PDN TSTI1 FILT+ GNDA HSIN– FLYP HSIN+ FLYC +VCP_FILT HS_CLAMP2 FLYN HS_CLAMP1 Top-Down (Through Package ) View 48-Pin QFN Package GNDCP GNDHS Figure 1-2. QFN Pin Diagram...

  • Page 5: Pin Descriptions

    CS42L42 1.3 Pin Descriptions 1.3 Pin Descriptions Table 1-1. Pin Descriptions Power Internal State at Pin Name Pin Description Driver Receiver Pin # Pin # Supply Connection Reset Microphone HS_CLAMP1 Headset Depletion FET Connections. Input to drain of — —...
  • Page 6 CS42L42 1.3 Pin Descriptions Table 1-1. Pin Descriptions (Cont.) Power Internal State at Pin Name Pin Description Driver Receiver Pin # Supply Connection Reset Pin # I/O I C Input/Output. I C input and output. — CMOS Hysteresis Input open-drain...

  • Page 7: Electrostatic Discharge (Esd) Protection Circuitry

    1.4 Electrostatic Discharge (ESD) Protection Circuitry 1.4 Electrostatic Discharge (ESD) Protection Circuitry ESD-sensitive device. The CS42L42 is manufactured on a CMOS process. Therefore, it is generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while handling and storing this device.
  • Page 8 CS42L42 1.4 Electrostatic Discharge (ESD) Protection Circuitry Table 1-2. ESD Domains (Cont.) Signal Name (CSP/QFN) Topology Domain (See * in Topology Figures for Pad) VCP/ GNDA Substrate (GNDA) GNDHS GNDA HS_CLAMP1 HS_CLAMP2 HSBIAS_FILT HSBIAS_FILT_REF HSIN+ +VCP_FILT/–VCP_FILT Domain HSIN– VP/GNDA Domain...

  • Page 9: Typical Connections

    CS42L42 2 Typical Connections 2 Typical Connections CS42L42 Headset Connector WAKE P_ W VL_SEL RING_SENSE Note 1 Battery DIGLDO_PDN TIP_SENSE VL or VP DIGLDO_PDN 1.8 V 1.8 V/1.2 V (3.0–5.0 V) and VL_SEL HPSENSB Configurations HPOUTB Headphone VD_FILT HPOUTA Output Filter HPSENSA 2.2 µF...
  • Page 10 CS42L42 2 Typical Connections CS42L42 _____ Headset Connector WAKE Note 1 RING_SENSE VL_SEL Battery VL or VP 1.8 V 1.8 V/1.2 V TIP_SENSE DIGLDO_PDN (3.0–5.0 V) DIGLDO_PDN and VL_SEL HPOUTB Headphone Configurations VD_FILT HPOUTA Output Filter VL or VP 2.2 µF...

  • Page 11: Electromagnetic Compatibility (Emc) Circuitry

    CS42L42 2.1 Electromagnetic Compatibility (EMC) Circuitry 2.1 Electromagnetic Compatibility (EMC) Circuitry The circuit in Fig. 2-3 may be applied to signals not local to the CS42L42 (i.e., that traverse significant distances) for EMC. To/from To/from DUT other Notes: circuits L1 and L2: Ferrite: = 30–100 MHz...

  • Page 12: Characteristics And Specifications

    VP < 3.0 V: HSBIAS, charge pump LDO, TIP_SENSE threshold, RING_SENSE threshold. 4.The maximum over/undervoltage is limited by the input current. 5.Table 1-1 lists the power supply domain in which each CS42L42 pin resides. 6.±VCP_FILT is specified in Table 3-16.
  • Page 13 CS42L42 3 Characteristics and Specifications Table 3-4. Output Fault Rating Test conditions: GNDA =GNDCP= 0 V; VA =1.8 V; VP =3.6 V; voltages are with respect to ground. Source Fault Supply Expected Years HPOUT(A,B) GNDA +VCP_FILT –VCP_FILT HS3/HS4 (HSx switch to ground)
  • Page 14 CS42L42 3 Characteristics and Specifications Table 3-8. DAC High-Pass Filter (HPF) Characteristics Test conditions (unless specified otherwise) Analog and digital gains are all set to 0 dB; T = +25°C. Parameter Minimum Typical Maximum Unit Passband –0.05-dB corner — 0.180x10 –3...
  • Page 15 CS42L42 3 Characteristics and Specifications Table 3-11. Wind-Noise Digital Filter Characteristics Test conditions (unless specified otherwise): MCLK = 12 MHz; MCLK_SRC_SEL = 0; Fs = 48 kHz; ADC HPF disabled. Parameters Minimum Typical Maximum Unit Passband –3.0-dB corner ADC_WNF_CF = 000 —...
  • Page 16 Fig. 2-2 show CS42L42 connections; input is a full-scale 1-kHz sine wave; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; parameters and can vary with VA; typical performance data taken with VL = VA = 1.8 V, VP = 3.6 V; min/max performance data taken with VA = 1.66–1.94 V;...
  • Page 17 Fig. 2-2 show CS42L42 connections; input test signal is a 24-bit full-scale 997-Hz sine wave with 1 LSB of triangular PDF dither applied; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; parameters can vary with VA; typical performance data taken with VL = VA = 1.8 V, VP = 3.6 V;...
  • Page 18 Fig. 2-2 show CS42L42 connections; GNDHS = GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; parameters can vary with VA and VP; typical performance data taken with VL = VA = 1.8 V, VP = 3.6 V; min/max performance data taken with VA = 1.66–1.94 V, VL = 1.8 V, VP = 3.0–5.25;...
  • Page 19 Fig. 2-1 shows CS42L42 connections; GNDA = GNDP = GNDCP = GNDD = 0 V; voltages are with respect to ground; parameters can vary with VA and VP; typical performance data taken with VL = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with Normal Mode VA = 1.66–1.94 V;...
  • Page 20 CS42L42 3 Characteristics and Specifications 6.Condition 1 transition timing. HS_BIAS_CTRL/ “1.86/2.0/2.3 V” “Hi - Z/0” DETECT_MODE 1.86/2.0/ mb-tran 2.3 V HS_BIAS Voltage Hi-Z 7.Condition 2 transition timing. “2.3 V” “1.86 V” HS_BIAS_CTRL/ HS_BIAS_CTRL/ “2.0 V/2.3 V” “1.86 V” “2.0 V”...
  • Page 21 Test conditions (unless specified otherwise): Fig. 2-1 Fig. 2-2 show CS42L42 connections; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; VL = VCP = VA = 1.8 V, VP = 3.6 V; T = +25°C.
  • Page 22 Fig. 2-1 Fig. 2-2 show CS42L42 connections; input test signal held low (all zero data); GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; VL = VA = 1.8 V, VP = 3.6 V; T = +25°C.
  • Page 23 Test conditions (unless specified otherwise): Fig. 2-1 shows CS42L42 connections; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; performance data taken with VA = VCP = VL = 1.8 V; DIGLDO_PDN is deasserted; VP = 3.6 V; T = +25°C;...
  • Page 24 Fig. 2-1 shows CS42L42 connections; GNDA = GNDL = GNDCP = 0 V; voltages are with respect to ground; parameters can vary with VA and VP; typical performance data taken with VL = VA = 1.8 V, VP = 3.6 V; min/max performance data taken with VA = 1.66–1.94 V, VL = 1.8 V, VP = 3.0–5.25 V;...
  • Page 25 CS42L42 3 Characteristics and Specifications Table 3-21. Switching Specifications—SoundWire Port (Cont.) Test conditions (unless specified otherwise): GND = 0 V; SWIRE_SEL pin = VL; voltages are with respect to ground; VD_FILT = 1.2 V; VA = 1.8 V; VP = 3.6 V; TA = +25°C; logic 0 = ground, logic 1 = VL; input timings are measured at V and V thresholds;...
  • Page 26 CS42L42 3 Characteristics and Specifications Table 3-22. Digital Audio Interface Timing Characteristics Test conditions (unless specified otherwise): GNDA = GNDL = GNDCP = 0 V; all voltages with respect to ground; values are for both VL = 1.2 and 1.8 V;...
  • Page 27 = +25°C; SDA load capacitance equal to maximum value of C = 400 pF; minimum SDA pull-up resistance, R Table 3-1 P(min) describes some parameters in detail. All specifications are valid for the signals at the pins of the CS42L42 with the specified load capacitance. Parameter Symbol Minimum...
  • Page 28 Fig. 2-1 shows CS42L42 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; parameters can vary with VL and VP; min/max performance data taken with VCP = VA = 1.8 V, VD_FILT = 1.2 V; VP = 3.0–5.25 V; VL = 1.66–1.94 V (VL_SEL = VP) or VL = 1.1–1.3 V (VL_SEL = GNDD);...

  • Page 29: Functional Description

    Figure 4-1. Overview of Signal Flow The CS42L42 is an ultralow-power, 24-bit audio codec, with a single analog input ADC channel and a stereo DAC. The ADC is fed by fully differential or pseudodifferential analog input that support mic and line-level input signals. The DAC feeds a stereo pseudodifferential output amplifier.
  • Page 30 4.13. • The CS42L42 supports plug presence-detect capability via the two associated sense pins: TIP_SENSE and RING_ SENSE. The sense pins are debounced to filter out brief events before being reported to the corresponding presence detect bit and generating an interrupt if appropriate. Plug presence detection is described in Section 4.14.

  • Page 31: Analog Input

    ADC on loud passages. If the gain is too low to avoid clipping, sounds may be too low and SNR may suffer. The CS42L42 ADC path achieves very high dynamic range with a very low noise floor with minimal power. Using patent-pending circuitry that simplifies the ADC input-path configuration, the ADC fundamentally captures the entire sound signal.

  • Page 32: Digital Mixer

    CS42L42 4.2 Digital Mixer 4.1.4 Soft Ramping Control ADC_SOFTRAMP_EN (see 153) is set, changes to ADC digital volumes are applied slowly by stepping through each volume-control setting with a delay between steps equal to an integer number of Fs periods. The delay between steps can...

  • Page 33: Three-Band Equalizer

    CS42L42 4.3 Three-Band Equalizer 4.2.2 Mixer Attenuation Values The digital mixer contains programmable attenuation blocks that are configured as described in the MIXER_CHx_VOLy field descriptions in Section 7.15.1—Section 7.15.3. For all settings except 0 dB, attenuation on the mixer input includes an offset that increases as attenuation increases, as follows: For commonly used –6n dB (n 1, 2, etc.}) attenuation settings, the offset rounds the attenuation exactly to the...
  • Page 34 CS42L42 4.3 Three-Band Equalizer To avoid audible distortion when inputs to the equalizer are extremely large, the gain must be limited to 0 dB for each filter stage and all B coefficients must be between ±1.0. Table 4-2 shows, coefficients are represented in binary by 32-bit signed values stored in S1.30 two’s complement format.
  • Page 35 CS42L42 4.3 Three-Band Equalizer Example 4-1. Writing the EQ Filter Coefficients (Cont.) 7 Clear the EQ write enable bit. Equalizer Filter Coefficient Read/Write 0x00 Reserved 0000 00 — EQ_WRITE Disable EQ write. EQ_READ Disable EQ read. 0x01 8 Set the EQ filter start bit.

  • Page 36: Analog Output

    CS42L42 4.4 Analog Output 4.4 Analog Output This section describes the headphone (HP) outputs. The CS42L42 provides an analog output that is fed from the mixer. Fig. 4-7 shows the general flow of the analog outputs. DAC Data Path +VCP_FILT...
  • Page 37 4.4 Analog Output 4.4.2 Using External Output Switches The CS42L42 can work with external switches for the headphone outputs along with mic inputs. Fig. 4-10 shows a simplified, closed-loop example of supporting two separate headsets, including headphone and mic support. For simplicity, tip sense and ring sense connectivity is not shown.
  • Page 38 REF connection point is also at the connector in the closed-loop configuration, which improves HP performance over the open-loop method. Together, the closed-loop configuration results in the best performance if switches must be used. 4.4.4 Output Load Detection The CS42L42 can distinguish between the following output loads: • = 15, 30, or 3 k •...

  • Page 39: System Headphone Parasitic Resistances

    HP_LD_EN is set (see 148), the CS42L42 proceeds to detect the resistance and capacitance of the output load. A 24-kHz tone is output on HPOUTA, and HS3 or HS4 (depending on China headset detect results) is measured using an internal resistor bank as a reference.
  • Page 40 CS42L42 4.5 System Headphone Parasitic Resistances Fig. 4-12 shows the headphone-to-analog input electrical path. From HPOUTA From HPOUTB COM2 HSBIAS_ FILT_REF HS3_REF BIAS HS_BIAS HSBIAS_ HSIN– FILT HSIN+ Figure 4-12. Headphone-to-ADC Electrical Path Based on Fig. 4-12, the formula in Eq.

  • Page 41: Class H Amplifier

    Figure 4-14. Class H Operation The CS42L42 HP output amplifiers use a Cirrus Logic four-mode Class H technology, which maximizes operating efficiency of the typical Class AB amplifier while maintaining high performance. In a Class H amplifier design, the rail voltages supplied to the amplifier vary with the needs of the music passage being amplified.
  • Page 42 ±VCP/3, respectively. For these settings, the rail voltages supplied to the output stages are held constant, regardless of the signal level. In these settings, the CS42L42 amplifiers operate in a traditional Class AB configuration. 4.6.1.2 Adapt-to-Output Signal (ADPTPWR = 111) If ADPTPWR = 111, the rail voltage sent to the amplifiers is based only on whether the signal sent to the amplifiers would cause the amplifiers to clip when operating on the lower set of rail voltages at certain threshold values.
  • Page 43 CS42L42 4.6 Class H Amplifier 4.6.2 Power-Supply Transitions Charge-pump transitions from the lower to the higher set of rail voltages occur on the next FLYN/FLYP clock cycle. Despite the system’s fast response time, the VCP_FILT pin’s capacitive elements prevent rail voltages from changing instantly.
  • Page 44 –2.5 V Figure 4-16. VCP_FILT Hysteresis—Headphone Output 4.6.3 Efficiency As discussed in previous sections, amplifiers internal to the CS42L42 operate from one of four sets of rail voltages, based on the needs of the signal being amplified. Fig. 4-17 Fig. 4-18 show power curves for all modes of operation and provides details regarding the power supplied to 15- and 30-stereo loads versus the power drawn from the supply for...
  • Page 45 CS42L42 4.6 Class H Amplifier Mode 0: 2.5 V Mode 1: VCP Mode 2: VCP/2 Mode 3: VCP/3 Adapt−to−Signal Mode 0.01 Power Delivered to Load (mW) Figure 4-17. Class H Power-to-Load Versus Power from Supply (15 , Stereo) The Adapt-to-Signal Mode trace in Fig.

  • Page 46: Clocking Architecture

    GNDA/GNDCP Figure 4-19. HP Short-Circuit Setup 4.7 Clocking Architecture The CS42L42 offers several ways to support control, ASP operation, data conversion, and signal processing. Internal clocks are generated either from SCLK (ASP_SCLK/SWIRE_CLK) or from the integrated fractional-N PLL; see Fig.
  • Page 47 4-20, functions as the default clock for the digital core of the CS42L42, during which time SCLK is unavailable. A reset event always returns it to running off of the RCO. If SCLK is unavailable, RCO clocking must be used only for I C functionality.
  • Page 48 Fractional-N PLL The CS42L42 has an integrated fractional-N PLL to support the clocking requirements of the internal analog circuits and converters. This PLL can be enabled or bypassed to suit system-clocking needs. The input reference clock for the PLL is the ASP_SCLK/SWIRE_CLK input pin.
  • Page 49 CS42L42 4.7 Clocking Architecture Table 4-6. Common PLL Setting Examples (Cont.) SCLK MCLK_SRC_SEL SCLK_PREDIV PLL_DIV_INT PLL_DIV_FRAC PLL_MODE PLL_DIVOUT MCLK PLL_CAL_RATIO (MHz) (see 136) (see 139) (see 147) (see 147) (see 147) (see 147) (MHz) (see 147) 4.00 0x2D 0x28 8CE7 0x10 11.2896...
  • Page 50 CS42L42 4.7 Clocking Architecture Table 4-6. Common PLL Setting Examples (Cont.) SCLK MCLK_SRC_SEL SCLK_PREDIV PLL_DIV_INT PLL_DIV_FRAC PLL_MODE PLL_DIVOUT MCLK PLL_CAL_RATIO (MHz) (see 136) (see 139) (see 147) (see 147) (see 147) (see 147) (MHz) (see 147) 0x39 0xAB 52B5 0x11 11.2896...
  • Page 51 CS42L42 4.7 Clocking Architecture 4.7.3.2 PLL Power-Up Sequence (Example: SCLK = 12 MHz and MCLKINT = 24 MHz) In this example, SCLK = 12 MHz and MCLK = 24 MHz. 1. Set SCLK_PREDIV to Divide-by-4 Mode (0x02). 2. Set PLL_DIVOUT to Divide-by-16 Mode (0x10). This reflects a value of n = 2, because the PLL_CAL_RATIO generated by Eq.

  • Page 52: Soundwire Interface

    To power down the PLL, clear PLL_START. 4.8 SoundWire Interface The MIPI-compliant SoundWire slave interface transports control and audio data. The external SoundWire master interface communicates with the CS42L42 SoundWire slave using SWIRE_SD and SWIRE_CLK (described in Table 1-1), which are shared with all devices on the SoundWire bus. The interface is an alternative to the ASP and I C interfaces for audio and control-data transfer.
  • Page 53 CS42L42 4.8 SoundWire Interface Fig. 4-23 shows examples of frame organization. 12 MHz, 10 columns, 50 rows, 48 kHz framerate 12.288 MHz, 8 columns, 64 rows, 48 kHz framerate GAP 7x2 GAP 1x2 48 kHz CH1 48 kHz 192 kHz LEFT 192 kHz LEFT 16 bits 96 kHz...
  • Page 54 CS42L42 4.8 SoundWire Interface Fig. 4-24 shows field assignments for each command. Table 4-8 lists similar information, with explanations for each field. Command Ping PREQ OPCODE[2:0] — BREQ BREL SlvStat_11[1:0] SlvStat_10[1:0] SlvStat_9[1:0] SlvStat_8[1:0] Command owner Master Attached Master Slave 11...
  • Page 55 Note: For accesses within the range 0x1000–0x1FFF, the COMMAND_OK response is specific to the CS42L42. The MIPI SoundWire Specification 1.0 requires a COMMAND_ IGNORED response to be returned instead of the COMMAND_OK.
  • Page 56 If attached to the SoundWire Bus, the CS42L42 constantly monitors the static and dynamic synchronization words of each frame to verify it is still in sync with the bus. If the CS42L42 detects two bit errors in the synchronization words within two SoundWire frames, it drops off the SoundWire bus and becomes unattached.
  • Page 57 CS42L42 4.8 SoundWire Interface 4.8.7 Payload Transport This section introduces describes how payload data is organized within a SoundWire frame and the control registers that define where each port’s payload data is located in the frame. Fig. 4-25 shows examples of how the data is positioned.
  • Page 58 The payload subwindow is the subset of a payload window where the port’s data resides, as controlled by the block-spacing mode. • There are two types of payload data: — Normal payload (isochronous payload streams) — Flow-controlled (asynchronous payload streams)—Not supported on the CS42L42. 4.8.8 Prepare/Enable Control The programming model of the state diagram of Fig. 4-27 must be followed to enable each channel within a port.
  • Page 59 MIPI SoundWire Specification and others are implementation specific. Table 4-10 lists base addresses for the SoundWire control and data ports implemented on the CS42L42. Table 6-1 shows how the SoundWire register space fits into the CS42L42 register map.
  • Page 60 CS42L42 4.8 SoundWire Interface Changing banked register values in the active bank for some registers can cause unpredictable behavior (e.g., changing payload location in the middle of the frame). When updating banked registers, the bank switch mechanism must be used to apply the changes on the next frame boundary.
  • Page 61 CS42L42 4.8 SoundWire Interface Section 4.8.12.2 Section 4.8.12.3 describe procedures for accessing registers outside the SoundWire IP. These apply only to access to registers above address 0x1000. SoundWire registers within the address range 0x0000–0x0FFF can be accessed directly without special procedures.
  • Page 62 Stop Mode is as follows: 1. The CS42L42 does not automatically change any functional states when going through the clock-stop process. As a result, if any function needs to be shut down or reconfigured, the master must first send the appropriate commands to configure the device Clear SCLK_PRESENT.
  • Page 63 7. Immediately after Step 6, the master sends a stopping frame. The master owns all payload bits and must drive the data pin on the last bit slot to a physical low level. The CS42L42 does not drive payload bits associated with data ports.
  • Page 64 CS42L42 4.8 SoundWire Interface 4.8.15 Configuration Guidelines with Examples Ex. 4-3 Ex. 4-4 describe configurations for programming three data ports for 48- and 96-kHz operations, each with 24-bit data. Data Port 1 has one 24-bit channel; Data Ports 2 and 3 have two channels each.
  • Page 65 One sample every second frame for a 24-kHz rate. N times the SoundWire frame length One sample every Nth frame, generating a 48/N-kHz rate. 8 kHz is the minimum rate for the CS42L42. Running all ports with 44.1 kHz requires a different SoundWire clock or frame shape that matches 44.1 kHz along with adjusting other parameters accordingly.
  • Page 66 CS42L42 4.8 SoundWire Interface 0 Control 0 DP1_ 0 Control 0 DP1_ Word Word 4 DP2_ 4 DP2_ 0DP2_ 0DP2_ 12 DP3_ 12 DP3_ 0DP3_ 0DP3_ 32 DP1_ 36 DP2_ 0DP2_ 44 DP3_ 0DP3_ 4-3: 48-kHz Sample Interval Rate 4-4: 96-kHz Sample Interval Rate Figure 4-29.

  • Page 67: Audio Serial Port (Asp)

    CS42L42 4.9 Audio Serial Port (ASP) 4.9 Audio Serial Port (ASP) The CS42L42 has an ASP to communicate audio and voice data between system devices, such as application processors and Bluetooth transceivers. ASP_SCLK_EN (see 138) must be set whenever DAO and DAI are used. The ASP can be configured to TDM, I S, and left justified (LJ) audio interfaces.
  • Page 68 CS42L42 4.9 Audio Serial Port (ASP) Table 4-15. Supported Serial-Port Sample Rates Serial Port Sample Rate (kHz) SCLK Frequency (MHz) 8.0 11.025 11.029 12 16 22.05 22.059 24 44.1 44.118 48 88.2 88.235 176.4 176.471 192 6.144 — — —...
  • Page 69 CS42L42 4.9 Audio Serial Port (ASP) FSYNC_PULSE_WIDTH_LB FSYNC_PULSE_WIDTH_UB (see 137) control the number of SCLK periods for which the LRCK signal is held high during each frame. Like the LRCK period, the LRCK-high width is programmable in single SCLK periods, from at least one period to at most the LRCK period minus one. That is, the LRCK-high width must be shorter than the LRCK period.
  • Page 70 CS42L42 4.9 Audio Serial Port (ASP) Table 4-16. ASP Channel Controls Channel Resolution MSB Location LSB Location ASP Transmit Channel 1 ASP_TX_CH1_RES ASP_TX_BIT_CH1_ST_MSB ASP_TX_BIT_CH1_ST_LSB ASP Transmit Channel 2 ASP_TX_CH2_RES ASP_TX_BIT_CH2_ST_MSB ASP_TX_BIT_CH2_ST_LSB ASP Receive DAI0 Channel 1 ASP_RX0_CH1_RES ASP_RX0_CH1_BIT_ST_MSB ASP_RX0_CH1_BIT_ST_LSB ASP Receive DAI0 Channel 2...
  • Page 71 CS42L42 4.9 Audio Serial Port (ASP) In NSB Mode, a null-remove block deletes samples that have a zero null sample indicator bit, restoring the stream’s original sample rate. Furthermore, the output data has the least-significant 8 bits of nonaudio data removed. Samples with a zero null sample indicator bit are removed from the data stream as invalid, null samples.
  • Page 72 CS42L42 4.9 Audio Serial Port (ASP) ASP_STP setting (see 138) determines which LRCK/FSYNC phase starts a frame in 50/50 Mode, as follows: • If ASP_STP = 0, the frame begins when LRCK/FSYNC transitions from high to low. See Fig. 4-37.

  • Page 73: S/Pdif Tx Port

    The CS42L42 does not decode or interpret samples chosen for retransmission. Additionally, the S/PDIF path does not incorporate any SRCs in the data path. When the data source comes from the TDM source, the CS42L42 selects between data from the DAI0 or DAI1 as follows: •...
  • Page 74 CS42L42 4.10 S/PDIF Tx Port SPDIF_LRCK_SRC_SEL(see 136) selects the S/PDIF LRCK source. SPDIF_LRCK_CPOL (see 137) sets polarity. Configuration bits mentioned above must be programmed before powering up the DAI ports and the S/PDIF transmit port. 4.10.2 S/PDIF, Headphone, and ADC Simultaneous Clocking Configuration S/PDIF transmission requires an SCLK of 128 x Fs supplied either from the ASP_SCLK/SWIRE_CLK input pin or from the internal fractional-N PLL.

  • Page 75: Sample-Rate Converters (Srcs)

    SPDIF_TX pin while the system is in a low power state. This allows an external S/PDIF receiver to remain locked to the S/PDIF stream from the CS42L42 and resume playback without delay if an output stream is later opened.

  • Page 76: Headset Interface

    The headset interface, shown in Fig. 4-42, is a collection of low-power circuits within the CS42L42’s ADC data path. It provides an intelligent interface to an external headset. It also communicates with an applications processor to relay command and status information.
  • Page 77 CS42L42 4.12 Headset Interface The interface generates HSBIAS, a programmable ultrahigh PSRR headset bias output for an external microphone. A low-voltage headset bias supply (VP = 3.0–3.2 V range) mode is supported. Signaling to the headset to set its operating...

  • Page 78: Headset Type Detect

    CS42L42 4.13 Headset Type Detect 4.13 Headset Type Detect The CS42L42 can detect whether headset Pins 3 and 4 are either the mic or ground signal and can set the appropriate connections via internal switches, as shown in Fig. 4-43.

  • Page 79: Plug Presence Detect

    GNDHS_ 4.14 Plug Presence Detect The CS42L42 uses TIP_SENSE and RING_SENSE to detect plug presence. The sense pins are debounced to filter out brief events before being reported to the corresponding presence-detect bit and generating an interrupt if appropriate. 4.14.1 Plug Types The plug-sense scheme supports the following plug types: •...
  • Page 80 The CS42L42 includes a RING_SENSE impedance-detection circuit to aid in the decision to use the RING_SENSE input pin as a HP ground reference.
  • Page 81 CS42L42 4.14 Plug Presence Detect 4.14.4 Tip-Sense and Ring-Sense Debounce Settings Fig. 4-45 shows the tip-sense and ring-sense controls and the associated interrupt, status, and mask registers. Headset Interface Block TIP_SENSE_PLUG p. 141 Interrupt Handler Block TIP_SENSE_UNPLUG p. 141 Tip Sense/Ring Sense...

  • Page 82: Power-Supply Considerations

    CS42L42 4.15 Power-Supply Considerations Interrupt status (see Section 7.6.12) does not contain an event-capture latch—a read always yields the current condition. Table 4-25 describes the plug/unplug status for both tip and ring. Table 4-25. Tip and Ring Plug/Unplug Status Plug Status...
  • Page 83 Full chip functionality 4.15.1 VP Monitor The CS42L42 voltage comparator monitors the VP power supply for potential brown-out conditions due to power-supply overload or other fault conditions. To perform according to specifications, VP is expected to remain above 3.0 V at all times.

  • Page 84: Control-Port Operation

    C Write of Page Address The first byte sent to the CS42L42 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write) in the LSB. To communicate with the CS42L42, the chip address field must match 1_0010, followed by the state of the AD1 and AD0 pins.
  • Page 85 CS42L42 4.16 Control-Port Operation Each byte is separated by an acknowledge (ACK) bit, which the CS42L42 outputs after each input byte is read and is input to the CS42L42 from the microcontroller after each transmitted byte. For write operations, the bytes following the MAP byte are written to the CS42L42 register addresses pointed to by the last received MAP address, plus however many autoincrements have occurred.

  • Page 86: Reset

    Send 10010(AD1)(AD0)1 (chip address and read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. 4.17 Reset The CS42L42 offers the reset options described in Table 4-29. Table 4-29. Reset Summary Reset Cause...

  • Page 87: Interrupts

    SoundWire interrupts and corresponding mask registers. Note that, unlike other interrupts implemented on the CS42L42, SoundWire interrupt mask bits are masked if cleared, rather than if set. Table 4-31. SoundWire Interrupt Status Registers and Corresponding Mask Registers—Page 0x00...
  • Page 88 CS42L42 4.18 Interrupts Table 4-32. Interrupt Status Registers and Corresponding Mask Registers—0x13 Interrupt Source Status Register Interrupt Mask Register ADC Overflow Interrupt Status (Section 7.6.1) ADC Overflow Interrupt Status (Section 7.6.1) Mixer Interrupt Status (Section 7.6.2) Mixer Interrupt Mask (Section 7.6.14)

  • Page 89: System Applications

    5.1 Power-Up Sequence Ex. 5-1 is the procedure for implementing HP playback from the ASP. This example sequence configures the CS42L42 for SCLK = 12.288 MHz, LRCK = 48 kHz, and TDM playback, in Slave Mode. Example 5-1. Power-Up Sequence...
  • Page 90 CS42L42 5.1 Power-Up Sequence Example 5-1. Power-Up Sequence (Cont.) EGISTER IELDS ALUE ESCRIPTION 4.8 Configure the ASP ASP Clock Configuration 1. 0x1207 0x00 clock. — Reserved ASP SCLK disabled. ASP_SCLK_EN ASP_HYBRID_MODE LRCK is an input from an external source. ASP_SCPOL_IN_ADC SCLK input drive polarity for ADC is normal.
  • Page 91 CS42L42 5.1 Power-Up Sequence Example 5-1. Power-Up Sequence (Cont.) EGISTER IELDS ALUE ESCRIPTION Enable SCLK. ASP Clock Configuration 1. 0x1207 0x20 — Reserved ASP SCLK enabled. ASP_SCLK_EN ASP_HYBRID_MODE LRCK is an input generated from SCLK. ASP_SCPOL_IN_ADC SCLK input drive polarity for ADC is normal.

  • Page 92: Power-Down Sequence

    CS42L42 5.2 Power-Down Sequence 5.2 Power-Down Sequence Ex. 5-2 is the procedure for powering down the HP playback. Example 5-2. Power-Down Sequence EGISTER IELDS ALUE ESCRIPTION 1 . Configure the DAC/Mixer Channels. 1.1 Mute Mixer A input. Mixer Channel A Input Volume. 0x2301...

  • Page 93: Soundwire Power Sequences

    Ex. 5-3 is the procedure for implementing ADC record, HP playback, and S/PDIF Tx playback from SoundWire. This sequence configures the CS42L42 for SWIRE_CLK = 12.288 MHz, 48-kHz sample interval rate, and a 64 x 8 SoundWire frame, as described in 4-3.
  • Page 94 CS42L42 5.3 SoundWire Power Sequences Example 5-3. SoundWire Power-Up Sequence (Cont.) EGISTER IELDS ALUE ESCRIPTION 10 Power up the codec. Power Down Control 0x1101 0xD2 ASP_DAO_PDN ASP output path is powered down. ASP_DAI_PDN ASP input path is powered down. MIXER_PDN Mixer is powered up.
  • Page 95 ADC record, HP playback, and S/PDIF Tx playback from SoundWire. This example sequence is a minimum configuration specifically for 4-3. This sequence configures the CS42L42 for SWIRE_CLK = 12.288 MHz, 48-kHz sample-interval rate, and 64 x 8 SoundWire frame, as described in 4-3.
  • Page 96 12 Prepare for clock stop now SCP System Control (Section 7.1.4) 0x0045 0x01 Reserved 0000 — WAKE_UP_ENABLE Asynchronous wake disabled. CLOCK_STOP_MODE Slave must not lose context in Clock Stop Mode. Reserved — CLOCK_STOP_PREPARE The CS42L42 is notified to prepare for clock stop. DS1083F2...

  • Page 97: X30 Read Sequence

    SCLK bypass as default mode and switches to PLL output after it settles. PLL start-up time is a maximum of 1 ms. 5.6 Standby Mode and Headset Clamps When the CS42L42 enters Standby Mode, headset clamps must first be disabled—HS_CLAMP_DISABLE = 1, see 136.
  • Page 98 CS42L42 5.7 Detection Sequence from Wake Example 5-5. Headset Type and Load-Detection Sequence (Cont.) EGISTER IELDS ALUE ESCRIPTION 7 Read the detect interrupt status registers. Monitor the HPDETECT_ Detect Interrupt Status 0x1309 0xXX PLUG and HPDETECT_ HSBIAS_SENSE Section 7.6.7 for decode.
  • Page 99 CS42L42 5.7 Detection Sequence from Wake Example 5-5. Headset Type and Load-Detection Sequence (Cont.) EGISTER IELDS ALUE ESCRIPTION 11.9 Configure HS DET Headset Detect Control 1. 0x111F 0x77 comparator reference HSDET_COMP2_LVL 0111 Reference level is set to 2.00 V. levels.
  • Page 100 CS42L42 5.7 Detection Sequence from Wake Example 5-5. Headset Type and Load-Detection Sequence (Cont.) EGISTER IELDS ALUE ESCRIPTION 17 Enable the HPOUT ground clamp DAC Control 2. 0x1F06 0x02 and configure the HP pull-down HPOUT_PULLDOWN 0000 0.9 k HPOUT_LOAD †...

  • Page 101: Vd_Filt/Vl Esd Diode

    5.9 External Output Switch Considerations The CS42L42 headset interface can be used with two external switches tying HPOUTA/B to HPSENSA/B, thus using a closed-loop method that enables the headphone amplifier to include the switch impedance in its feedback point. This method can improve output performance if the guidelines listed in Section 4.4.2...

  • Page 102: Register Quick Reference

    CS42L42 6 Register Quick Reference 6 Register Quick Reference Table 6-1 lists the register page addresses for each module. Section 4.8.9 describes how the page value maps to the address field (RegAddr[15:0]) for SoundWire read/write commands. Table 6-1. Register Base Addresses...

  • Page 103: Soundwire Address Maps

    — 0x00C0 General Interrupt Status 1 Register CS42L42-defined interrupt status 0x00C1 General Interrupt Mask 1 Register None CS42L42-defined interrupt enable mask 0x00C2 General Interrupt Status 2 Register CS42L42-defined interrupt status 0x00C3 General Interrupt Mask 2 Register None CS42L42-defined interrupt enable mask 0x00C4–0x00CF Reserved...

  • Page 104: Slave Control Port Registers

    CS42L42 6.2 Slave Control Port Registers 6.2 Slave Control Port Registers Slave Control Port Registers Address Function 0x0000–0x003F Reserved — 0x0040 SCP Interrupt — PORT3_ PORT2_ PORT1_ — GEN_INT_ STAT_BUS_ STAT_PARITY Status CASCADE CASCADE CASCADE CASCADE CLASH R/W1C p. 117...

  • Page 105: Slave Data Port 1-3, 15 Registers

    CS42L42 6.3 Slave Data Port 1–3, 15 Registers Slave Control Port Registers Address Function 0x00D0 Memory Access — LAST_LATE CMD_IN_ CMD_DONE RDATA_RDY Status PROGRESS — p. 122 0x00D1 Memory Access — LATE_RESP Control — p. 122 0x00D2 Memory Access —...

  • Page 106: Global Registers

    CS42L42 6.4 Global Registers Slave Data Port 1–3, 15 Registers Address Function +0x24 DPn Offset OFFSET1 Control 1 p. 126 +0x25 DPn Offset OFFSET2 Control 2 p. 126 +0x26 DPn Horizontal HSTART HSTOP Control p. 126 +0x27 DPn Block Control 3 —...

  • Page 107: Power-Down And Headset-Detect Registers

    CS42L42 6.5 Power-Down and Headset-Detect Registers 6.5 Power-Down and Headset-Detect Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94(Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x11—Power-Down and Headset-Detect Registers Address Function 0x00 Control Port Page PAGE Power Down Control 1 ASP_DAO_ ASP_DAI_...

  • Page 108: Clocking Registers

    CS42L42 6.6 Clocking Registers 6.6 Clocking Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x12—Clocking Registers Address Function 0x00 Control Port Page PAGE MCLK Source Select MCLKDIV MCLK_SRC_ 0x01 — p. 136 S/PDIF Clock...
  • Page 109 CS42L42 6.7 Interrupt Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x13—Interrupt Registers Address Function Detect Status 1 (Read HSBIAS_ TIP_SENSE_ TIP_SENSE_ — 0x09 Only) SENSE PLUG UNPLUG p. 141 Detect Status 2 (Read...

  • Page 110: Fractional-N Pll Registers

    CS42L42 6.8 Fractional-N PLL Registers 6.8 Fractional-N PLL Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x15—Fractional-N PLL Registers Address Function 0x00 Control Port Page PAGE PLL Control 1 PLL_START 0x01 — p. 146...

  • Page 111: Headset Bias Registers

    CS42L42 6.11 Headset Bias Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x1B—Headset Interface Registers Address Function 0x70 HSBIAS Sense and HSBIAS_ AUTO_ TIP_SENSE_ — HSBIAS_SENSE_TRIP Clamp Autocontrol SENSE_EN HSBIAS_HIZ p. 148 0x71 Wake Control...

  • Page 112: Dac Registers

    CS42L42 6.13 DAC Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x1D—ADC Registers Address Function ADC Volume ADC_VOL 0x03 p. 153 ADC Wind-Noise Filter — ADC_WNF_CF ADC_WNF_ ADC_HPF_CF ADC_HPF_EN 0x04 and HPF Control p. 154 0x05–0x7F Reserved...

  • Page 113: Equalizer Registers

    CS42L42 6.17 Equalizer Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x23—Mixer Volume Registers Address Function 0x04–0x7F Reserved — 6.17 Equalizer Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x24—Equalizer Registers...

  • Page 114: Src Registers

    CS42L42 6.19 SRC Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x25—AudioPort Interface Registers Address Function Serial Port Transmit SP_TX_ SP_TX_NSB_POS SP_TX_NFS_ SP_TX_ISOC_MODE 0x05 Isochronous Control RSYNC NSBB p. 159 Serial Port Transmit SP_TX_FS 0x06 —...

  • Page 115: Serial Port Transmit Registers

    CS42L42 6.22 Serial Port Transmit Registers 6.22 Serial Port Transmit Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x29—Serial Port Transmit Registers Address Function 0x00 Control Port Page PAGE ASP Transmit Size and ASP_TX_2FS...

  • Page 116: Id Registers

    CS42L42 6.24 ID Registers C Address: 10010(AD1)(AD0)[R/W] through 10010(AD1)(AD0)0 = 0x94 (Write); 10010(AD1)(AD0)1 = 0x95 (Read) Page 0x2A—Serial Port Receive Registers Address Function ASP Receive DAI0 ASP_RX0_ 0x09 — Channel 3 Bit Start CH3_BIT_ST_ p. 166 ASP Receive DAI0 ASP_RX0_CH3_BIT_ST_LSB...

  • Page 117: Soundwire Control Port 0 Registers

    CS42L42 7.1 SoundWire Control Port 0 Registers 7.1 SoundWire Control Port 0 Registers 7.1.1 SCP Interrupt Status 1 Address Base + 0x40 PORT3_ PORT2_ PORT1_ GEN_INT_ STAT_BUS_ — — STAT_PARITY CASCADE CASCADE CASCADE CASCADE CLASH R/W1C R/W1C Default Bits Name Description —...
  • Page 118 Clock stop prepare. Indicates whether the SoundWire master intends to stop the SoundWire clock. See Section 4.8.13. STOP_ 0 (Default) Clock stop not requested. PREPARE 1 The CS42L42 is notified to prepare for clock stop. 7.1.5 SCP Device Number Address Base + 0x46 — GROUP_ID DEVICE_NUMBER —...
  • Page 119 Name Description MIPI_MANUFACTURER_ MIPI manufacturer’s device ID upper byte. (Cirrus Logic is 0x01FA). The value is returned only if [15:8] enumeration is ON. A zero is returned if enumeration is OFF. If enumeration goes OFF due to a SoundWire bus clash in the middle of a read, a partial value may be returned.
  • Page 120 CS42L42 7.1 SoundWire Control Port 0 Registers 7.1.10 SCP Device ID 4 Address Base + 0x54 PART_ID [7:0] (DeviceID[15:8]) Default Bits Name Description PART_ID[7:0] Part ID lower byte. Unique ID for each device. The value can be read only while the SoundWire Slave is in the (DeviceID[15:8]) Enumeration ON state.
  • Page 121 CS42L42 7.1 SoundWire Control Port 0 Registers Bits Name Description — Reserved SCP_IMP_ SCP implementation defined 1. The combined interrupt from the interrupt controller is connected to this bit. DEF1 0 (Default) Interrupt not asserted. 1 Interrupt condition asserted 7.1.14 General Interrupt Mask 1 Address Base + 0xC1 —...
  • Page 122 CS42L42 7.1 SoundWire Control Port 0 Registers 7.1.17 Memory Access Status Address Base + 0xD0 — LAST_LATE CMD_IN_PROGRESS CMD_DONE RDATA_RDY — Default Bits Name Description — Reserved LAST_LATE Last command late. Indicates whether the previous read command completed in time for the response to be included in a single command for direct access.

  • Page 123: Soundwire Data Port (1-3) Descriptions

    CS42L42 7.2 SoundWire Data Port (1–3) Descriptions 7.1.19 Memory Access Timeout Address Base + 0xD2 — TIMEOUT_DISABLE TIMEOUT_CTRL — Default Bits Name Description — Reserved TIMEOUT_ Timeout disable. Disables timeout control. See Section 4.8.12 for details and examples. DISABLE 0 (Default) Timeout enabled on internal memory access through the APB memory bridge.
  • Page 124 CS42L42 7.2 SoundWire Data Port (1–3) Descriptions Bits Name Description STAT_ Status test/fail. Indicates whether an error was detected during PRBS, Static0, or Static1 test modes when a sink data port TEST_ (Data Ports 2 and 3) does not receive the expected value from the SoundWire bus. This bit is never set in source data ports FAIL (Data Port 1).
  • Page 125 CS42L42 7.2 SoundWire Data Port (1–3) Descriptions 7.2.5 DPn Prepare Status Address Base + 0x04 — NOT_FINISHED_CHANNEL2 NOT_FINISHED_CHANNEL1 Default Bits Name Description — Reserved NOT_ Not finished channel. Indicates whether each channel completed its state transition after the corresponding PREPARE_ FINISHED_ CHANNELx bit is written to prepare or deprepare the channel.
  • Page 126 CS42L42 7.2 SoundWire Data Port (1–3) Descriptions 7.2.9 DPn Sample Control 2 Address Base + 0x23 Address Base + 0x33 (Banked) SAMPLE_INTERVAL_HIGH Default Bits Name Description SAMPLE_ Sample interval upper byte. The interval is calculated in units of bit slots according to the following formula:...

  • Page 127: Global Registers

    Alpha revision. CS42L42 alpha revision level. AREVID and MTLREVID form the complete device revision ID (e.g.,: A0, B2). 0x00 … 0xFF 3:0 MTLREVID Metal revision. CS42L42 metal revision level. AREVID and MTLREVID form the complete device revision ID (e.g.,: A0, B2). 0x00 … 0xFF...
  • Page 128 CS42L42 7.3 Global Registers 7.3.5 Freeze Control Address 0x1006 — FREEZE Default Bits Name Description — Reserved FREEZE Freeze registers. Configures a hold on all volume-control and power-down register settings except PDN_MIC_LVL_DETECT 150). Use this bit only during normal operation after all circuit blocks in use have powered up. Using the bit when an affected circuit block is powering up could cause the change to occur immediately when power up completes (i.e., not gated by the...
  • Page 129 CS42L42 7.3 Global Registers 7.3.8 MCLK Control Address 0x1009 — INTERNAL_FS — Default Bits Name Description — Reserved INTERNAL_ Internal sample rate ( ). Selects the divide ratio from MCLK to produce the internal sample rate for all converters. Table 4-6 for programming details.

  • Page 130: Power Down And Headset Detects

    CS42L42 7.4 Power Down and Headset Detects Bits Name Description I2C_SCL_ C SCL debounce count enable. DBNC_EN Note: The settings of I2C_SDA_DBNC_EN and I2C_SCL_DBNC_EN must be identical. 0 (Default) Disabled. Must be 0 for Fast Mode or Fast-Plus Mode. 1 Enabled 7.3.12 I...
  • Page 131 CS42L42 7.4 Power Down and Headset Detects Bits Name Description ADC_ ADC power down 0 Powered up. The ADC is powered up. 1 (Default) The ADC is powered down. — Reserved PDN_ Codec power down. Configures the entire codec’s power state except for PLL_START and SPDIF_TX_PDN (which is not affected in order to support Keep-Alive Mode).
  • Page 132 CS42L42 7.4 Power Down and Headset Detects 7.4.3 Power Down Control 3 Address 0x1103 — SW_CLK_STP_STAT_SEL — VPMON_PDNB RING_SENSE_PDNB — Default Bits Name Description — Reserved SoundWire clock-stop status selection. Sets which functional blocks report as powered down before clearing...
  • Page 133 CS42L42 7.4 Power Down and Headset Detects 7.4.5 Ring Sense Control 2 Address 0x1105 TS_RS_GATE — Default Bits Name Description TS_RS_ Tip/ring sense gating, Configures whether tip and ring sense are interdependent. Section 4.14.4 gives programming details. GATE 0 (Default) Individual jacks. TIP_SENSE and RING_SENSE are independent of each other.
  • Page 134 CS42L42 7.4 Power Down and Headset Detects 7.4.9 Tip Sense Control 1 Address 0x1113 TS_INV — TS_FALL_DBNCE_TIME TS_RISE_DBNCE_TIME Default Bits Name Description TS_INV Tip sense raw signal invert. Used to invert the raw signal from the tip-sense circuit. Reverses the meaning of...
  • Page 135 CS42L42 7.4 Power Down and Headset Detects 7.4.12 Headset Detect Control 2 Address 0x1120 HSDET_CTRL HSDET_SET HSBIAS_REF — HSDET_AUTO_TIME Default Bits Name Description 7:6 HSDET_ Headset type detect mode. Sets the headset type detect mode. For details, see Section 4.13.1.

  • Page 136: Clocking Registers

    HS_CLAMP_DISABLE Default Bits Name Description — Reserved Headset clamp disable. Clamping devices suppress ground-noise when connecting to an external amplifier and the CS42L42 CLAMP_ is powered down. Section 5.6 gives a programming example. This bit is affected by LATCH_TO_VP (see 150).
  • Page 137 CS42L42 7.5 Clocking Registers Bits Name Description SPDIF_ S/PDIF LRCK polarity. Selects LRCK polarity. See Section 4.10.1. LRCK_ 0 (Default) Normal CPOL 1 Inverted — Reserved 7.5.3 FSYNC Pulse Width, Lower Byte Address 0x1203 FSYNC_PULSE_WIDTH_LB Default Bits Name Description FSYNC_ FSYNC pulse width LB.
  • Page 138 CS42L42 7.5 Clocking Registers 7.5.7 ASP Clock Configuration 1 Address 0x1207 — ASP_SCLK_EN ASP_HYBRID_MODE ASP_SCPOL_IN_ADC ASP_SCPOL_IN_DAC ASP_LCPOL_OUT ASP_LCPOL_IN Default Bits Name Description — Reserved ASP_SCLK_ ASP SCLK enable. Must be set if DAO/DAI functionality is used. 0 (Default) Disabled 1 Enabled ASP_ ASP Hybrid-Master Mode.

  • Page 139: Interrupt Registers

    CS42L42 7.6 Interrupt Registers 7.5.10 Input ASRC Clock Select Address 0x120A — CLK_IASRC_SEL Default Bits Name Description — Reserved CLK_IASRC_ Input ASRC clock select. Selects input ASRC MCLK frequency. See Section 4.11 for programming details. 00 (Default) 6 MHz 01 12 MHz...
  • Page 140 CS42L42 7.6 Interrupt Registers Bits Name Description EQ_OVFL Digital equalizer data path overflow. Indicates the overrange status of the equalizer data path. Rising-edge state transitions may cause an interrupt, depending on the programming of the associated interrupt mask bit. 0 No digital clipping occurred in the equalizer data path.
  • Page 141 CS42L42 7.6 Interrupt Registers 7.6.5 ASP TX Interrupt Status Address 0x1305 — ASPTX_SMERROR ASPTX_LATE ASPTX_EARLY ASPTX_NOLRCK Default Bits Name Description — Reserved ASPTX_ ASP TX SM error. Determines whether the transmit state machine cannot retrieve data from output buffers; it is analogous SMERROR to ASP Rx request overload.
  • Page 142 CS42L42 7.6 Interrupt Registers 7.6.8 Detect Interrupt Status 2 Address 0x130A DETECT_TRUE_ DETECT_FALSE_ SHORT_ SHORT_ — HSBIAS_HIZ FALSE TRUE RELEASE DETECTED Default Bits Name Description DETECT_TRUE_FALSE Mic detect True-to-False. Indicates whether the mic level detector transitions from True to False.
  • Page 143 CS42L42 7.6 Interrupt Registers 7.6.10 VP Monitor Interrupt Status Address 0x130D — VPMON_TRIP Default Bits Name Description — Reserved VPMON_TRIP VP monitor interrupt. If the VP power supply falls below 2.6 V, this bit is set. See Section 4.15.1 for details.
  • Page 144 CS42L42 7.6 Interrupt Registers 7.6.14 Mixer Interrupt Mask Address 0x1317 M_EQ_ — M_EQ_OVFL M_MIX_CHA_OVFL M_MIX_CHB_OVFL BIQUAD_OVFL Default Bits Name Description — Reserved M_EQ_BIQUAD_OVFL EQ_BIQUAD_OVFL mask. 0 Unmasked 1 (Default) Masked M_EQ_OVFL EQ_OVFL mask. 0 Unmasked 1 (Default) Masked M_MIX_CHA_OVFL MIXER_CHx_OVFL mask.
  • Page 145 CS42L42 7.6 Interrupt Registers 7.6.17 ASP TX Interrupt Mask Address 0x131A — M_ASPTX_SMERROR M_ASPTX_LATE M_ASPTX_EARLY M_ASPTX_NOLRCK Default Bits Name Description — Reserved M_ASPTX_ ASPTX_SMERROR mask. SMERROR 0 Unmasked 1 (Default) Masked M_ASPTX_ ASPTX_LATE mask. LATE 0 Unmasked 1 (Default) Masked M_ASPTX_ ASPTX_EARLY mask.

  • Page 146: Fractional-N Pll Registers

    CS42L42 7.7 Fractional-N PLL Registers 7.6.20 VP Monitor Interrupt Mask Address 0x131E — M_VPMON_TRIP Default Bits Name Description — Reserved VP monitor mask. VPMON_ 0 Unmasked. Unmask/enable this bit only when VP exceeds the detection voltage threshold; applicable to power-up TRIP conditions or if VP is not at its steady-state voltage.
  • Page 147 CS42L42 7.7 Fractional-N PLL Registers 7.7.2 PLL Division Fractional Bytes 0–2 Address 0x1502–0x1504 0x1502 PLL_DIV_FRAC[7:0] 0x1503 PLL_DIV_FRAC[15:8] 0x1504 PLL_DIV_FRAC[23:16] Default Bits Name Description PLL_DIV_ PLL fractional portion of divide ratio LSB. See Section 4.7.3 for details. There are 3 bytes of PLL feedback divider fraction –17...

  • Page 148: Hp Load-Detect Registers

    CS42L42 7.8 HP Load-Detect Registers 7.8 HP Load-Detect Registers 7.8.1 Load-Detect R/C Status Address 0x1925 — CLA_STAT — RLA_STAT Default Bits Name Description Reserved — CLA_STAT Capacitor load-detection result for HPA. See Section 4.4.4 for details. Note: Low capacitance results were determined with C = 1 nF;...
  • Page 149 2.Before unmasking status, pending wake events must be cleared via WAKEB_CLEAR. They are also cleared when deactivating and then reactivating the relevant mode using DETECT_MODE (see 150). A powered-down device using the CS42L42 does not respond to the associated detect wake event. 7.9.3 ADC Disable Mute Address 0x1B72 ADC_DISABLE_S0_MUTE —...
  • Page 150 DETECTED mask is cleared and remains high while the SHORT_DETECTED mask is set. 10 Reserved 11 Normal Mode. HSBIAS output uses a high-performance reference for 2.0- or 2.7-V Mode. See HSBIAS_CTRL. If LATCH_TO_VP = 1, PDN_ALL = 1 overrides DETECT_MODE setting and powers down the CS42L42. HSBIAS_ HS bias output control.
  • Page 151 CS42L42 7.9 Headset Interface Registers Bits Name Description EVENT_ Event status selection. Selects the level of processing on readable status originating in the VP supply domain. STATUS_ 0 (Default) Raw (unprocessed) status events are selected. 1 Sticky processed status events are selected.

  • Page 152: Headset Bias Registers

    CS42L42 7.10 Headset Bias Registers 7.9.10 Detect Interrupt Mask 1 Address 0x1B79 M_HSBIAS_SENSE M_TIP_SENSE_PLUG M_TIP_SENSE_UNPLUG — Default Interrupt mask register bits serve as a mask for the interrupt sources in the interrupt status registers. Interrupts are described in Section 4.18.

  • Page 153: Adc Registers

    CS42L42 7.11 ADC Registers Bits Name Description HSBIAS_ HSBIAS pull down. Used to enable a 60-k pulldown on HS bias. 0 (Default) Pulldown resistor off 1 Pulldown resistor on Reserved — HSBIAS_ HSBIAS ramp rate. Sets bidirectional output ramp rate between ground and set level. See Table 3-15 for specifications.

  • Page 154: Dac Control Registers

    CS42L42 7.12 DAC Control Registers 7.11.4 ADC Wind-Noise Filter and HPF Address 0x1D04 ADC_WNF_CF ADC_WNF_EN ADC_HPF_CF ADC_HPF_EN Default Bits Name Description — Reserved ADC_ ADC wind-noise filter select. Sets the corner frequency for the wind-noise filter. See Section 4.1.2 for details.

  • Page 155: Hp Control Register

    CS42L42 7.13 HP Control Register 7.13 HP Control Register 7.13.1 HP Control Address 0x2001 — ANA_MUTE_B ANA_MUTE_A FULL_SCALE_VOL — Default Bits Name Description — Reserved ANA_MUTE_ Analog mute Channel B. See Section 4.4 for details. 0 Unmuted 1 (Default) Muted ANA_MUTE_ Analog mute Channel A.

  • Page 156: Equalizer

    CS42L42 7.16 Equalizer 7.15.2 Mixer ADC Input Volume Address 0x2302 — MIXER_ADC_VOL Default Bits Name Description — Reserved MIXER_ Mixer input attenuation. Sets the attenuation level to be applied to various stereo digital inputs. See Section 4.2 for details. ADC_ Each mixer input can be muted or attenuated from –62 to 0 dB in 1-dB steps...
  • Page 157 CS42L42 7.16 Equalizer 7.16.3 Equalizer Filter Coefficient Output 0–3 Address 0x2407–0x240A EQ_COEF_OUT[7:0] EQ_COEF_OUT[15:8] EQ_COEF_OUT[23:16] EQ_COEF_OUT[31:24] Default Bits Name Description 31:0 EQ coefficient out. Coefficient read data from the equalizer. Data read from the equalizer filter coefficient pointed to by the COEF_ coefficient address pointer.

  • Page 158: Audioport Interface Registers

    CS42L42 7.17 AudioPort Interface Registers 7.17 AudioPort Interface Registers 7.17.1 Serial Port Receive Channel Select Address 0x2501 — SP_RX_CHB_SEL SP_RX_CHA_SEL Default Bits Name Description — Reserved SP_RX_ SP RX Channel B select for DAI0. Selects right input channel. Valid only if the SWIRE_SEL pin is deasserted.See...
  • Page 159 CS42L42 7.17 AudioPort Interface Registers 7.17.4 S/PDIF Channel Select Address 0x2504 — SPDIF_CHB_SEL SPDIF_CHA_SEL Default Bits Name Description — Reserved SPDIF_ S/PDIF Channel B select for DAI0. Selects right input channel. Valid only if the SWIRE_SEL pin is deasserted. See CHB_SEL Section 4.10.1...

  • Page 160: Src Registers

    CS42L42 7.18 SRC Registers 7.17.7 S/PDIF/SoundWire Control 1 Address 0x2507 SW_RES_INPUT SW_RES_OUTPUT — SPDIF_RES Default Bits Name Description — Reserved SPDIF_RES S/PDIF channel resolution. See Section 4.10.1 for programming details. 00 20 bits 01 16 bits 10 24 bits 11 (Default) 32 bits SW_RES_ ADC channel resolution when using SoundWire.

  • Page 161: S/Pdif

    S/PDIF keep alive. Transmit state depends on the SPDIF_TX_DIGEN and SPDIF_TX_PDN settings. See Table 4-20. TX_KAE Note: The value of this field has no function on the CS42L42. SPDIF_ S/PDIF TX power-down. TX_PDN 0 Transmit state depends on the SPDIF_TX_DIGEN and SPDIF_TX_PDN settings. See Table 4-20.

  • Page 162: Serial Port Register Transmit Registers

    CS42L42 7.21 Serial Port Register Transmit Registers Bits Name Description SPDIF_ Validity. Affects the validity flag (V) bit 28, transmitted in each subframe in conjunction with the SPDIF_TX_VCFG setting. TX_V 0 (default) enables the S/PDIF transmitter to maintain connection during error or mute conditions.
  • Page 163 CS42L42 7.21 Serial Port Register Transmit Registers 7.21.2 ASP Transmit Channel Enable Address 0x2902 — ASP_TX_CH2_EN ASP_TX_CH1_EN Default Bits Name Description — Reserved ASP_ ASP Transmit Channel 2 enable. Although two output channels exist, data from Channel 1 is replicated onto Channel 2 if ASP_ TX_CH2_EN is set.

  • Page 164: Serial Port Receive Registers

    CS42L42 7.22 Serial Port Receive Registers 7.21.6 ASP Transmit Hi-Z and Delay Configuration Address 0x2906 — ASP_TX_DRV_Z ASP_TX_HIZ_DLY — Default Bits Name Description — Reserved ASP_TX_ ASP transmit drive to Hi-Z. SDA value for unselected bits. DRV_Z 00 (Default) Hi-Z...
  • Page 165 CS42L42 7.22 Serial Port Receive Registers 7.22.2 ASP Receive DAI0 Channel 1 Phase and Resolution Address 0x2A02 — ASP_RX0_CH1_AP — ASP_RX0_CH1_RES Default Bits Name Description — Reserved ASP_RX0_ ASP receive DAI0 active phase. Valid only in 50/50 Mode (ASP_5050 = 1 and ASP_RXx_2FS = 0).
  • Page 166 CS42L42 7.22 Serial Port Receive Registers 7.22.7 ASP Receive DAI0 Channel 2 Bit Start LSB Address 0x2A07 ASP_RX0_CH2_BIT_ST_LSB Default Bits Name Description 7:0 ASP_RX0_CH2_ ASP receive DAI0 Channel 2 bit start LSB. Configures the LSB location of the channel with respect to SOF (LRCK BIT_ST_LSB edge + phase lag).
  • Page 167 CS42L42 7.22 Serial Port Receive Registers 7.22.12 ASP Receive DAI0 Channel 4 Bit Start MSB Address 0x2A0C — ASP_RX0_CH4_BIT_ST_MSB Default Bits Name Description — Reserved ASP_RX0_CH4_ ASP receive DAI0 Channel 4 bit start MSB. Configures the MSB location of the channel with respect to SOF (LRCK...

  • Page 168: Id Registers

    + phase lag) 7.23 ID Registers 7.23.1 Subrevision Address 0x3014 SUBREVISION Default Bits Name Description Subrevision. Identifies the CS42L42 subrevision. The Page 0x30 read sequence in Section 5.4 must be followed to read SUBREVISION this register. 0000 0011 Initial version. DS1083F2...

  • Page 169: Pcb Layout Considerations

    8.3 QFN Thermal Pad The CS42L42 comes in a compact QFN package, the underside of which reveals a large metal pad that serves as a thermal relief to provide maximum heat dissipation. This pad must mate with a matching copper pad on the PCB and must be electrically connected to ground.

  • Page 170: Plots

    CS42L42 9 Plots 9 Plots 9.1 Digital Filter Response 9.1.1 Highpass Filter—ADC −0.5 −0.5 −1 −1 −1.5 −1.5 −2 −2 −2.5 −2.5 −3 −3 −3.5 −3.5 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 Normalised to Fs Normalised to Fs −3...
  • Page 171 CS42L42 9.1 Digital Filter Response 9.1.2 Highpass Filter—DAC −0.5 −1 −1.5 −2 −2.5 −3 −3.5 Normalised to Fs −3 x 10 Figure 9-5. DAC HPF Response 9.1.3 ADC, Notch Filter Disabled 0.25 −10 −20 0.15 −30 −40 0.05 −50 −0.05 −60...
  • Page 172 CS42L42 9.1 Digital Filter Response 9.1.4 ADC, Notch Filter Enabled 0.25 −10 −20 0.15 −30 −40 0.05 −50 −0.05 −60 −0.1 −70 −0.15 −80 −0.2 −90 −0.25 −100 0.05 0.15 0.25 0.35 0.45 frequency (Normalized to Fs) frequency (Normalized to Fs) Figure 9-10.
  • Page 173 CS42L42 9.1 Digital Filter Response 9.1.5 DAC to HP, Fs = 44.118 kHz, MCLK = 136 x LRCK −10 −20 −30 −40 −1 −50 −2 −60 −70 −3 −80 −4 −90 −100 −5 0.05 0.15 0.25 0.35 0.45 Frequency (Normalised to Fs) Frequency (Normalised to Fs) Figure 9-14.
  • Page 174 CS42L42 9.1 Digital Filter Response 9.1.6 DAC to HP, Fs = 48.000 kHz, MCLK = 125 x LRCK −10 −20 −30 −40 −1 −50 −2 −60 −70 −3 −80 −4 −90 −5 −100 0.05 0.15 0.25 0.35 0.45 Frequency (Normalised to Fs) Frequency (Normalised to Fs) Figure 9-19.
  • Page 175 CS42L42 9.1 Digital Filter Response 9.1.7 x_SDOUT and x_SDIN ASRC, Fs = 48 kHz 0.25 −10 −20 0.15 −30 −40 0.05 −50 −0.05 −60 −0.1 −70 −0.15 −80 −0.2 −90 −0.25 −100 0.05 0.15 0.25 0.35 0.45 frequency (Normalized to Fs) frequency (Normalized to Fs) Figure 9-24.

  • Page 176: Windnoise Filter Responses

    CS42L42 9.2 Windnoise Filter Responses 9.2 Windnoise Filter Responses −3 −6 −12 −36 −60 ADCx_WNF=000 ADCx_WNF=001 ADCx_WNF=010 ADCx_WNF=011 −84 ADCx_WNF=100 ADCx_WNF=101 ADCx_WNF=110 ADCx_WNF=111 0.0005 0.005 0.05 Frequency (normalized to Fs) Figure 9-28. Windnoise Filter Frequency Response −3 −6 −12 −36 −60...
  • Page 177 CS42L42 9.2 Windnoise Filter Responses ADCx_WNF=000 ADCx_WNF=001 ADCx_WNF=010 ADCx_WNF=011 ADCx_WNF=100 ADCx_WNF=101 −90 ADCx_WNF=110 ADCx_WNF=111 −180 −270 −360 0.0005 0.005 0.05 Frequency (normalized to Fs) Figure 9-30. Windnoise Filter Phase Response Windnoise Filter Phase Delay (Normalized) ADCx_WNF=000 ADCx_WNF=001 ADCx_WNF=010 ADCx_WNF=011 ADCx_WNF=100...

  • Page 178: Hsbias Current Sense Vs. Vp Voltage Per Trip Setting

    CS42L42 9.3 HSBIAS Current Sense vs. VP Voltage per Trip Setting 9.3 HSBIAS Current Sense vs. VP Voltage per Trip Setting Figure 9-32. HS Bias Current Sense vs. VP Voltage for Each Trip Setting (HS BIAS = 2-V Mode) DS1083F2...

  • Page 179: Package Dimensions

    CS42L42 10 Package Dimensions 10 Package Dimensions 10.1 WLCSP Package Dimensions Ball A1 Location Indicator (seen through package) Ball A 1 Location Indicator Øb Øddd Z X Y Seating Plane Øccc WAFER BACK SIDE SIDE VIEW BUMP SIDE Notes: • Dimensioning and tolerances per ASME Y 14.5M–1994.

  • Page 180: Qfn Package Dimensions

    CS42L42 10.2 QFN Package Dimensions 10.2 QFN Package Dimensions Table 10-2. QFN Package Dimensions Dimension Minimum Nominal Maximum 0.70 0.75 0.80 0.00 0.035 0.05 — 0.55 — 0.203 REF 0.15 0.20 0.25 6.00 BSC 0.40 BSC 6.00 BSC 0.35 0.40 0.45...

  • Page 181: Thermal Characteristics

    12 Ordering Information Table 12-1. Ordering Information Halogen Temperature Product Description Package Grade Container Order # Free Free Range CS42L42 Low-Power Audio 49-ball Extended –40 to +85°C Tape and reel CS42L42-CWZR Codec with WLCSP Commercial SoundWire™–I S/TDM 48-pin QFN Extended –40 to +85°C...

  • Page 182: Revision History

    “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties.
  • Page 183 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cirrus Logic CS42L42-CNZ CS42L42-CNZR...

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