Cirrus Logic CS42L42 Manual page 60

Changing banked register values in the active bank for some registers can cause unpredictable behavior (e.g., changing
payload location in the middle of the frame). When updating banked registers, the bank switch mechanism must be used
to apply the changes on the next frame boundary.
4.8.10.1 Bank Switch
Bank switching allows the master to change which of two register banks is active. This mechanism is used to enable
channels, change the SoundWire frame size, or rearrange payload data for all slaves and all ports at the same moment.
If any ports have a sample interval that spans multiple SoundWire frames, to avoid audio glitches, a bank switch must be
applied on a frame boundary that is also a stream-synchronization point (SSP).
The bank change is performed by writing to the SCP frame control register (see
It can be performed to all slave devices at once using the DevAddr = 15 group alias in the control word.
The recommended procedure to perform a bank switch while the data port is enabled and streaming is as follows:
1. Update configuration registers in the inactive bank of all active SoundWire ports with new configuration. If a setting
must remain the same, the inactive bank register must be programmed to the same value as the active bank.
2. In the frame preceding a normal SSP alignment, using the device address = 15 alias to all SoundWire slaves, write
to the inactive bank's SCP frame control register in either Bank 0 or Bank 1. This write causes the bank change to
occur on the next SoundWire frame boundary to the bank whose SCP frame control register was written.
4.8.11 SoundWire Data Port Map
Port 0 functions as SCP, which provides control for the slave.
the base addresses. Table 4-11
Table 4-12 describes the supported read/write characteristics for SoundWire bit fields.
Type
Read/Write
Read/Write/Modified
Read Only
Write One to Clear
Write Only
4.8.12 Advanced Peripheral Bus (APB) Bridge Access Procedures
Read/write commands to addresses 0x1000–0xFFFF outside the SoundWire IP pass through a translation bridge to the
device's internal APB. The APB protocol and delays through the bridge do not allow the commands to complete within the
SoundWire frame for all cases and require special procedures to perform read/write commands to this memory space. A
consequence of the delay through the bridge is that register writes to locations outside the SoundWire IP are not aligned
to a SoundWire frame boundary. Read-only status registers manage these transfers in the memory-access status and
memory-read-last-address registers (see
If an access is attempted through the bridge before the previous transfer completes (indicated by
see p. 122), a COMMAND_FAIL response is returned on the SoundWire bus. Otherwise, a COMMAND_OK response is returned
to acknowledge any other access through the bridge, regardless of whether the registers exist outside the SoundWire IP.
By default, a timeout occurs after 8 bus cycles.
is 0 bus cycles if TIMEOUT_DISABLE
RESP and M_TIMEOUT_ERR
DS1083F2
shows data-port mapping.
Table 4-11. Data Port Mapping
Data Port Resource Channel 2 Channel 1
Port 1 ADC
Port 2 DAC
Port 3 S/PDIF
Table 4-12. Register Bit Types
Abbreviation
R/W Register value can be read or written by software
RWM Register value can be read or written by software, or modified by hardware.
R/O Read-only status register, can be read but not written by software.
R/W1C Status register is cleared by software writing 1 to the bit.
W/O Write-only bits trigger an action when written, but its value cannot be read.
Section 7.1.17
TIMEOUT_CTRL (seep.
(see p. 123) is set. If issues arise in transferring information, unmasking
(see p. 121) allows timeout conditions to generate the corresponding interrupts.
Section
Section 6.1 lists each data port's registers,
— Channel A
Channel B Channel A
Channel B Channel A
Description
and Section 7.1.20).
123) can be used to extend this period. The period
CS42L42
4.8 SoundWire Interface
7.1.12) in either Bank 0 or Bank 1.
Table 4-10
CMD_IN_PROGRESS
M_LATE_
lists
= 1,
60