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114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver
Features
Eight 24-bit D/A, two 24-bit A/D Converters
114 dB DAC / 114 dB ADC Dynamic Range
-100 dB THD+N
System Sampling Rates up to 192 kHz
S/PDIF Receiver Compatible with EIAJ CP1201
and IEC-60958
Recovered S/PDIF Clock or System Clock
Selection
8:2 S/PDIF Input MUX
ADC High-pass Filter for DC Offset Calibration
Expandable ADC Channels and One-line Mode
Support
Digital Output Volume Control with Soft Ramp
Digital +/-15dB Input Gain Adjust for ADC
Differential Analog Architecture
Supports logic levels between 5 V and 1.8 V.
Preliminary Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
TXP
VARX
RXP0
RXP1/GPO1
RXP2/GPO2
RXP3/GPO3
RXP4/GPO4
Rx
RXP5/GPO5
RXP6/GPO6
RXP7/GPO7
GPO
M UTEC
M UTE
FILT+
VQ
Ref
REFGND
VA
AGND
AINL+
ADC#1
AINL-
AINR+
ADC#2
AINR-
AOUTA1+
AOUTA1-
AOUTB1+
AOUTB1-
AOUTA2+
AOUTA2-
AOUTB2+
AOUTB2-
AOUTA3+
AOUTA3-
AOUTB3+
AOUTB3-
AOUTA4+
AOUTA4-
AOUTB4+
AOUTB4-
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2005
General Description
The CS42528 codec provides two analog-to-digital and eight
digital-to-analog delta-sigma converters, as well as an integrat-
ed S/PDIF receiver, in a 64-pin LQFP package.
The CS42528 integrated S/PDIF receiver supports up to eight
inputs, clock recovery circuitry and format auto-detection. The
internal stereo ADC is capable of independent channel gain
control for single-ended or differential analog inputs. All eight
channels of DAC provide digital volume control and differential
analog outputs. The general purpose outputs may be driven
high or low, or mapped to a variety of DAC mute controls or
ADC overflow indicators.
The CS42528 is ideal for audio systems requiring wide dynam-
ic range, negligible distortion and low noise, such as A/V
receivers, DVD receivers, digital speaker and automotive audio
systems.
ORDERING INFORMATION
CS42528-CQZ
CS42528-DQZ
CDB42528
AGND
LPFLT
DGND VD
DGND
C&U Bit
Data Buffer
S/PDIF
Clock/Data
Decoder
Recovery
Form at
Detector
Internal M CLK
DEM
Digital Filter
Gain & Clip
ADC
Serial
Data
Digital Filter
Gain & Clip
DAC#1
DAC#2
DAC#3
DAC#4
DAC#5
DAC#6
DAC#7
DAC#8
(All Rights Reserved)
CS42528
-10° to 70° C 64-pin LQFP
-40° to 85° C 64-pin LQFP
Evaluation Board
VD
INT
RST
Control
AD0/CS
Port
AD1/CDIN
SDA/CDOUT
SCL/CCLK
VLC
OM CK
M ult/Div
RM CK
Serial
SAI_LRCK
Audio
SAI_SCLK
Interface
SAI_SDOUT
Port
VLS
ADCIN1
ADCIN2
CX_SDOUT
CX_LRCK
CX_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CODEC
Serial
CX_SDIN4
Port
Lead Free
Lead Free
JAN '05
DS586PP5
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Related Manuals for Cirrus Logic CDB42528
Summary of Contents for Cirrus Logic CDB42528
- Page 1 AOUTB4+ DAC#8 AOUTB4- This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Cirrus Logic, Inc. Copyright © Cirrus Logic, Inc. 2005 http://www.cirrus.com JAN ‘05 (All Rights Reserved)
-
Page 2: Table Of Contents
CS42528 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ................ 7 Specified Operating Conditions ....................7 Absolute Maximum Ratings ...................... 7 Analog Input Characteristics ..................... 8 A/D Digital Filter Characteristics ....................9 Analog Output Characteristics ....................10 D/A Digital Filter Characteristics ..................... 11 Switching Characteristics...................... - Page 3 CS42528 5. REGISTER QUICK REFERENCE ..................42 6. REGISTER DESCRIPTION ....................47 6.1 Memory Address Pointer (MAP) ..................47 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) ..........47 6.3 Power Control (address 02h).................... 48 6.4 Functional Mode (address 03h)..................49 6.5 Interface Formats (address 04h) ..................
- Page 4 CS42528 12. APPENDIX C: PLL FILTER ....................80 12.1 External Filter Components ................... 81 12.1.1 General ......................81 12.1.2 Jitter Attenuation ....................81 12.1.3 Capacitor Selection ................... 82 12.1.4 Circuit Board Layout ..................82 13. APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ....83 13.1 AES3 Receiver External Components ................
- Page 5 CS42528 Figure 42. Quad Speed Mode Transition Band................85 Figure 43. Quad Speed Mode Transition Band (Detail) ..............85 Figure 44. Quad Speed Mode Passband Ripple................85 Figure 45. Single Speed (fast) Stopband Rejection ..............86 Figure 46. Single Speed (fast) Transition Band ................86 Figure 47.
- Page 6 CS42528 LIST OF TABLES Table 1. Common OMCK Clock Frequencies ................26 Table 2. Common PLL Output Clock Frequencies................ 26 Table 3. Slave Mode Clock Ratios ....................26 Table 4. Serial Audio Port Channel Allocations................27 Table 5. DAC De-Emphasis ......................50 Table 6.
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Page 7: Characteristics And Specifications
CS42528 1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and = 25° C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz;... -
Page 8: Analog Input Characteristics
CS42528 ANALOG INPUT CHARACTERISTICS = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. -
Page 9: A/D Digital Filter Characteristics
CS42528 A/D DIGITAL FILTER CHARACTERISTICS Parameter Symbol Unit Single Speed Mode (2 to 50 kHz sample rates) Passband (-0.1 dB) (Note 5) 0.47 ±0.035 Passband Ripple Stopband (Note 5) 0.58 Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) 12/Fs ∆t µs... -
Page 10: Analog Output Characteristics
CS42528 ANALOG OUTPUT CHARACTERISTICS = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.;... -
Page 11: D/A Digital Filter Characteristics
CS42528 D/A DIGITAL FILTER CHARACTERISTICS Fast Roll-Off Slow Roll-Off Parameter Unit Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner 0.4535 0.4166 to -3 dB corner 0.4998 0.4998 Frequency Response 10 Hz to 20 kHz -0.01 +0.01... -
Page 12: Switching Characteristics
CS42528 SWITCHING CHARACTERISTICS (For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C = 30 pF) Parameters Symbol... -
Page 13: Switching Characteristics - Control Port - I C Format
CS42528 SWITCHING CHARACTERISTICS - CONTROL PORT - I C FORMAT (For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C = 30 pF) Parameter... -
Page 14: Switching Characteristics - Control Port - Spi Tm Format
CS42528 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C = 30 pF) Parameter Symbol... -
Page 15: Dc Electrical Characteristics
CS42528 DC ELECTRICAL CHARACTERISTICS = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) Parameter Symbol Units Power Supply Current normal operation, VA = VARX = 5 V (Note 22) VD = 5 V VD = 3.3 V µA Interface current, VLC=5 V (Note 23) VLS=5 V... -
Page 16: Digital Interface Characteristics
CS42528 DIGITAL INTERFACE CHARACTERISTICS (For CQZ, T = +25° C; For DQZ, T = -40 to +85° Parameters (Note 26) Symbol Units 0.7xVLS High-Level Input Voltage Serial Port 0.7xVLC Control Port 0.2xVLS Low-Level Input Voltage Serial Port 0.2xVLC Control Port VLS-1.0 High-Level Output Voltage at I =2 mA... -
Page 17: Pin Descriptions
CS42528 2. PIN DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CX_SDIN1 RXP1/G PO 1 CX_SCLK RXP2/G PO 2 CX_LRCK RXP3/G PO 3 RXP4/G PO 4 DGND RXP5/G PO 5 RXP6/G PO 6 SCL/CCLK RXP7/G PO 7 CS42528... - Page 18 CS42528 AD0/CS Address Bit 0 (I C)/Control Port Chip Select (SPI) (Input ) - AD0 is a chip address pin in I C mode; CS is the chip select signal in SPI mode. Interrupt (Output ) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts”...
- Page 19 CS42528 CX_SDOUT CODEC Serial Data Output ( Output ) - Output for two’s complement serial audio data from the internal and external ADCs. ADCIN1 External ADC Serial Input ( Input ) - The CS42528 provides for up to two external stereo analog to digital ADCIN2 converter inputs to provide a maximum of six channels on one serial data output line when the CS42528 is placed in One Line mode.
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Page 20: Typical Connection Diagram
CS42528 3. TYPICAL CONNECTION DIAGRAM + 3.3 V to + 5 V +5 V 0.01 µ F 0.1 µ F 0.1 µ F 0.01 µ F 10 µ F 10 µ F 0.01 µ F 0.1 µ F 0.1 µ F 0.01 µ... -
Page 21: Applications
CS42528 4. APPLICATIONS Overview The CS42528 is a highly integrated mixed signal 24-bit audio codec comprised of 2 analog-to-digital con- verters (ADC), implemented using multi-bit delta-sigma techniques, 8 digital-to-analog converters (DAC) and a 192 kHz digital audio S/PDIF receiver. Other functions integrated within the codec include indepen- dent digital volume controls for each DAC, digital de-emphasis filters for DAC and S/PDIF, digital gain control for ADC channels, ADC high-pass filters, an on-chip voltage reference, and an 8:2 mux for S/PDIF sources. -
Page 22: High Pass Filter And Dc Offset Calibration
CS42528 4.2.2 High Pass Filter and DC Offset Calibration The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. The high pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. -
Page 23: Digital Volume And Mute Control
CS42528 4.3.3 Digital Volume and Mute Control Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to -127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h)”... -
Page 24: S/Pdif Receiver
A comprehensive buffering scheme provides read access to the channel status and user data. External components are used to terminate and isolate the incoming data cables from the CS42528. These components and required circuitry are detailed in the CDB42528. 4.4.1... -
Page 25: Clock Generation
CS42528 Clock Generation The clock generation for the CS42528 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input. -
Page 26: Omck System Clock Mode
CS42528 4.5.2 OMCK System Clock Mode A special clock switching mode is available that allows the clock that is input through the OMCK pin to be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock Con- trol (address 06h)”... -
Page 27: Digital Interfaces
CS42528 Single Speed Double Speed Quad Speed One Line Mode #1 SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x 128x Table 3. Slave Mode Clock Ratios Digital Interfaces 4.6.1 Serial Audio Interface Signals The CS42528 interfaces to an external Digital Audio Processor via two independent serial ports, the CODEC serial port, CODEC_SP and the Serial Audio Interface serial port, SAI_SP. - Page 28 CS42528 Serial Inputs / Outputs CX_SDIN4 left channel DAC #7 right channel DAC #8 one line mode DAC channels 7,8 CX_SDOUT left channel ADC #1 right channel ADC #2 one line mode ADC channels 1,2,3,4,5,6 SAI_SDOUT left channel S/PDIF Left or ADC #1 right channel S/PDIF Right or ADC #2 one line mode...
-
Page 29: Serial Audio Interface Formats
CS42528 4.6.2 Serial Audio Interface Formats The CODEC_SP and SAI_SP digital audio serial ports support 5 formats with varying bit depths from 16 to 24 as shown in Figures 10 to 14. These formats are selected using the configuration bits in the registers, “Functional Mode (address 03h)”... -
Page 30: Figure 11. Left Justified Serial Audio Formats
CS42528 CX_LRCK Left Channel Right Channel SAI_LRCK CX_SCLK SAI_SCLK CX_SDINx -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1 CX_SDOUT SAI_SDOUT Left Justified Mode, Data Valid on Rising Edge of SCLK Bits/Sample SCLK Rate(s) Notes... -
Page 31: Figure 13. One Line Mode #1 Serial Audio Format
CS42528 64 clks 64 clks CX_LRCK SAI_LRCK Left Channel Right Channel CX_SCLK SAI_SCLK CX_SDIN1 DAC1 DAC3 DAC5 DAC2 DAC4 DAC6 20 clks 20 clks 20 clks 20 clks 20 clks 20 clks DAC7 DAC8 CX_SDIN4 20 clks 20 clks ADC1 ADC3 ADC5 ADC2... -
Page 32: Adcin1/Adcin2 Serial Data Format
CS42528 4.6.3 ADCIN1/ADCIN2 Serial Data Format The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port configuration register bit settings. -
Page 33: One Line Mode(Olm) Configurations
CS42528 4.6.4 One Line Mode(OLM) Configurations 4.6.4a OLM Config #1 One Line Mode Configuration #1 can support up to 8 channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data. This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. -
Page 34: Olm Config #2
CS42528 4.6.4b OLM Config #2 This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and no channels of S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 96 kHz on all chan- nels for both the DAC and ADC. -
Page 35: Olm Config #3
CS42528 4.6.4c OLM Config #3 This One Line Mode configuration #3 will support up to 8 channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. -
Page 36: Olm Config #4
CS42528 4.6.4d OLM Config #4 This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and no channels of S/PDIF received data. OLM Config #4 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz. -
Page 37: Olm Config #5
CS42528 4.6.4e OLM Config #5 This One-Line Mode configuration can support up to 8 channels of DAC data, 2 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. -
Page 38: Control Port Description And Timing
CS42528 Control Port Description and Timing The control port is used to access the registers, allowing the CS42528 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. -
Page 39: I 2 C Mode
CS42528 4.7.2 C Mode In I C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. -
Page 40: Interrupts
CS42528 Send stop condition, aborting write. Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. - Page 41 FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and REFGND. The CDB42528 evaluation board demonstrates the optimum layout and power supply arrangements.
-
Page 42: Register Quick Reference
CS42528 5. REGISTER QUICK REFERENCE Addr Function Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 page 47 default Power Con- PDN_RCVR1 PDN_RCVR0 PDN_ADC PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 trol page 48 default Functional CODEC_FM1 CODEC_FM0 SAI_FM1 SAI_FM0 ADC_SP ADC_SP DAC_DEM RCVR_DEM Mode SEL1 SEL0... - Page 43 CS42528 Addr Function Channel B4_MUTE A4_MUTE B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE Mute page 59 default Vol. Control A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0 page 59 default Vol. Control B1_VOL7 B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0 page 59 default Vol.
- Page 44 CS42528 Addr Function ADC Left Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0 Ch. Gain page 62 default ADC Right Reserved Reserved RGAIN5 RGAIN4 RGAIN3 RGAIN2 RGAIN1 RGAIN0 Ch. Gain page 62 default RCVR Mode SP_SYNC Reserved DE-EMPH1 DE-EMPH0 INT1 INT0 HOLD1 HOLD0...
- Page 45 CS42528 Addr Function RXP6/GPO Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 70 default RXP5/GPO Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 70 default RXP4/GPO Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 70 default RXP3/GPO Mode1 Mode0 Polarity...
- Page 46 CS42528 Addr Function 3Ah - C or U Data CU Buffer7 CU Buffer6 CU Buffer5 CU Buffer4 CU Buffer3 CU Buffer2 CU Buffer1 CU Buffer0 Buffer page 72 default DS586PP5...
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Page 47: Register Description
CS42528 6. REGISTER DESCRIPTION All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, In- terrupt Status Register, and Q-Channel Subcode Bytes and C-bit or U-bit Data Buffer, which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. -
Page 48: Power Control (Address 02H)
CS42528 Power Control (address 02h) PDN_RCVR1 PDN_RCVR0 PDN_ADC PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 6.3.1 POWER DOWN RECEIVER (PDN_RCVRX) Default = 10 00 - Receiver and PLL in normal operational mode. 01 - Receiver and PLL held in a reset state. Equivalent to setting 11. 10 - Reserved. -
Page 49: Functional Mode (Address 03H)
CS42528 Functional Mode (address 03h) CODEC_FM1 CODEC_FM0 SAI_FM1 SAI_FM0 ADC_SP SEL1 ADC_SP SEL0 DAC_DEM RCVR_DEM 6.4.1 CODEC FUNCTIONAL MODE (CODEC_FMX) Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 192 kHz sample rates) 11 - Reserved Function:... -
Page 50: Interface Formats (Address 04H)
CS42528 in the Receiver Mode Control (address 1Eh) register to set the appropriate sample rate. DAC_DEM FRC_PLL_LK DE-EMPH[1:0] De-Emphasis reg03h[1] reg06h[0] reg1Eh[5:4] Mode No De-Emphasis Auto-Detect Fs Reserved 32 kHz 44.1 kHz 48 kHz Table 5. DAC De-Emphasis 6.4.5 RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM) Default = 0 Function: When enabled, de-emphasis will be automatically applied when emphasis is detected based on the... -
Page 51: Table 7. Digital Interface Formats
CS42528 DIF1 DIF0 Description Format Figure Left Justified, up to 24-bit data S, up to 24-bit data Right Justified, 16-bit or 24-bit data reserved Table 7. Digital Interface Formats 6.5.2 ADC ONE_LINE MODE (ADC_OLX) Default = 00 Function: These bits select which mode the ADC will use. By default one-line mode is disabled but can be se- lected using these bits. -
Page 52: Misc Control (Address 05H)
CS42528 6.5.5 CODEC RIGHT JUSTIFIED BITS (CODEC_RJ16) Default = 0 Function: This bit determines how many bits to use during right justified mode for the DAC and ADC within the CODEC Serial Port. By default the DAC and ADC will be in RJ24 bits but can be set to RJ16 bits. 0 - 24 bit mode. -
Page 53: Clock Control (Address 06H)
CS42528 6.6.5 HIGH PASS FILTER FREEZE (HPF_FREEZE) Default = 0 Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig- ital Filter Characteristics”... -
Page 54: Table 11. Omck Frequency Settings
CS42528 6.7.2 OMCK FREQUENCY (OMCK FREQX) Default = 00 Function: Sets the appropriate frequency for the supplied OMCK. OMCK Freq1 OMCK Freq0 Description 11.2896 MHz or 12.2880 MHz 16.9344 MHz or 18.4320 MHz 22.5792 MHz or 24.5760 MHz Reserved Table 11. OMCK Frequency Settings 6.7.3 PLL LOCK TO LRCK (PLL_LRCK) Default = 0... -
Page 55: Omck/Pll_Clk Ratio (Address 07H) (Read Only)
CS42528 OMCK/PLL_CLK Ratio (address 07h) (Read Only) RATIO7(2 RATIO6(2 RATIO5(2 RATIO4(2 RATIO3(2 RATIO2(2 RATIO1(2 RATIO0(2 6.8.1 OMCK/PLL_CLK RATIO (RATIOX) Default = xxxxxxxx Function: This register allows the user to find the exact absolute frequency of the recovered MCLK coming from the PLL. -
Page 56: Burst Preamble Pc And Pd Bytes (Addresses 09H - 0Ch)(Read Only)
CS42528 6.9.3 SYSTEM CLOCK SELECTION (ACTIVE_CLK) Default = x 0 - Output of PLL 1 - OMCK Function: This bit identifies the source of the internal system clock (MCLK). 6.9.4 RECEIVER CLOCK FREQUENCY (RCVR_CLKX) Default = xxx Function: The CS42528 will auto-detect the ratio between the OMCK and the recovered clock from the PLL, which is displayed in register 07h. -
Page 57: Volume Transition Control (Address 0Dh)
CS42528 6.11 Volume Transition Control (address 0Dh) Reserved SNGVOL SZC1 SZC0 AMUTE MUTE SAI_SP RAMP_UP RAMP_DN 6.11.1 SINGLE VOLUME CONTROL (SNGVOL) Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control register and the other Volume Control registers are ignored. - Page 58 CS42528 6.11.3 AUTO-MUTE (AMUTE) Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converters of the CS42528 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel.
-
Page 59: Channel Mute (Address 0Eh)
CS42528 6.12 Channel Mute (address 0Eh) B4_MUTE A4_MUTE B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE 6.12.1 INDEPENDENT CHANNEL MUTE (XX_MUTE) Default = 0 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converter outputs of the CS42528 will mute when enabled. The quiescent volt- age on the outputs will be retained. -
Page 60: Mixing Control Pair 1 (Channels A1 & B1)(Address 18H)
CS42528 6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h) Mixing Control Pair 2 (Channels A2 & B2)(address 19h) Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) Mixing Control Pair 4 (Channels A4 & B4)(address 1Bh) Px_A=B Reserved Reserved Px_ATAPI4 Px_ATAPI3... -
Page 61: Table 16. Atapi Decode
CS42528 6.15.2 ATAPI CHANNEL MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42528 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 16 and Figure 8 for additional information. ATAPI4 ATAPI3 ATAPI2... -
Page 62: Adc Left Channel Gain (Address 1Ch)
CS42528 6.16 ADC Left Channel Gain (address 1Ch) Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0 6.16.1 ADC LEFT CHANNEL GAIN (LGAINX) Default = 00h Function: The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and Zero Cross bits (SZC[1:0]) from +15 to -15 dB. -
Page 63: Receiver Mode Control 2 (Address 1Fh)
CS42528 6.18.2 DE-EMPHASIS SELECT BITS (DE-EMPHX) Default = 00 00 - Reserved 01 - De-Emphasis for 32 kHz sample rate. 10 - De-Emphasis for 44.1 kHz sample rate. 11 - De-Emphasis for 48 kHz sample rate. Function: Used to specify which de-emphasis filter to apply when the “Force PLL Lock (FRC_PLL_LK)” on page 54 is enabled. -
Page 64: Interrupt Status (Address 20H) (Read Only)
CS42528 TMUX2 TMUX1 TMUX0 Description Output from pin RXP6 Output from pin RXP7 Table 18. TXP Output Selection 6.19.2 RECEIVER MULTIPLEXER (RMUXX) Default = 000 Function: Selects which of the eight receiver inputs will be mapped to the internal receiver. RMUX2 RMUX1 RMUX0... -
Page 65: Interrupt Mask (Address 21H)
CS42528 6.20.4 D TO E U-BUFFER TRANSFER (DETU) Default = 0 Function: Indicates when the user status buffer has changed. 6.20.5 ADC OVERFLOW (OVERFLOW) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42528 ADC signal path. 6.20.6 RECEIVER ERROR (RERR) Default = 0 Function:... -
Page 66: Channel Status Data Buffer Control (Address 24H)
CS42528 01 - Falling edge active 10 - Level active 11 - Reserved 6.23 Channel Status Data Buffer Control (address 24h) Reserved LOCKM Reserved Reserved Reserved BSEL 6.23.1 SPDIF RECEIVER LOCKING MODE (LOCKM) Default = 1 0 - Revision C compatibility mode. 1 - Revision D default mode. -
Page 67: Receiver Channel Status (Address 25H) (Read Only)
CS42528 6.24 Receiver Channel Status (address 25h) (Read Only) AUX3 AUX2 AUX1 AUX0 AUDIO COPY ORIG The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control register. 6.24.1 AUXILIARY DATA WIDTH (AUXX) Default = xxxx Function:... -
Page 68: Receiver Errors (Address 26H) (Read Only)
CS42528 Function: A ‘0’ indicates that the received data is 1st generation or higher. A ‘1’ indicates that the received data is original. COPY and ORIG will both be set to ‘1’ if the incoming data is flagged as professional, or if the receiver is not in use. -
Page 69: Receiver Errors Mask (Address 27H)
CS42528 Indicates the received confidence status. This bit is updated on sub-frame boundaries. 6.25.6 BI-PHASE ERROR (BIP) Default = x 0 - No error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. Function: Indicates a bi-phase coding error. This bit is updated on sub-frame boundaries. 6.25.7 PARITY STATUS (PAR) Default = x 0 - No error... -
Page 70: Rxp/General Purpose Pin Control (Addresses 29H To 2Fh)
CS42528 0 - Channel mute is not mapped to the MUTEC pin 1 - Channel mute is mapped to the MUTEC pin Function: Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are mapped, then the MUTEC pin is driven to the "active"... - Page 71 CS42528 ignored. It is recommended that in this mode this bit be set to 0. 6.28.3 FUNCTIONAL CONTROL (FUNCTIONX) Default = 00000 Function: RXP Input - If the pin is configured for an RXP input, the functional bits are ignored. It is recommended that in this mode all the functional bits be set to 0.
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Page 72: Q-Channel Subcode Bytes 0 To 9 (Addresses 30H To 39H) (Read Only)
CS42528 6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only) Address3 Address2 Address1 Address0 Control3 Control2 Control1 Control0 Track7 Track6 Track5 Track4 Track3 Track2 Track1 Track0 Index7 Index6 Index5 Index4 Index3 Index2 Index1 Index0 Minute7 Minute6 Minute5 Minute4 Minute3... -
Page 73: Parameter Definitions
CS42528 7. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. -
Page 74: References
Digital Audio Transmission, by Clifton Sanchez.; an excellent tutorial on SCMS. It is available from the AES as preprint 3518. 6) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Con- verter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Con- vention of the Audio Engineering Society, September 1997. -
Page 75: Package Dimensions
CS42528 9. PACKAGE DIMENSIONS 64L LQFP PACKAGE DRAWING ∝ INCHES MILLIMETERS 0.55 0.063 1.40 1.60 0.002 0.004 0.006 0.05 0.10 0.15 0.007 0.008 0.011 0.17 0.20 0.27 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30 0.390 0.393 BSC 0.398 9.90 10.0 BSC 10.10 0.461... -
Page 76: Appendix A: External Filters
CS42528 10. APPENDIX A: EXTERNAL FILTERS 10.1 ADC Input Filter The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are ×... -
Page 77: Appendix B: S/Pdif Receiver
CS42528 11. APPENDIX B: S/PDIF RECEIVER 11.1 Error Reporting and Hold Function The UNLOCK bit indicates whether the PLL is locked to the incoming S/PDIF data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitude of the eye pattern opening, indicating a link that is close to generating errors. -
Page 78: Channel Status Data E Buffer Access
CS42528 8-bits 8-bits From S/PDIF Received words Receiver Data Buffer Control Port Figure 26. Channel Status Data Buffer Structure 11.2.1 Channel Status Data E Buffer Access The user can monitor the incoming Channel Status data by reading the E buffer, which is mapped into the register space of the CS42528, through the control port Data Buffer. -
Page 79: Serial Copy Management System (Scms)
CS42528 11.2.2 Serial Copy Management System (SCMS) The CS42528 allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately. 11.3 User (U) Data E Buffer Access Entire blocks of U data are buffered using a cascade of 2 block-sized RAMs to perform the buffering as described in the Channel Status section. -
Page 80: Appendix C: Pll Filter
CS42528 12. APPENDIX C: PLL FILTER The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update infor- mation to the PLL. This results in the PLL being immune to data dependent jitter effects because the S/PDIF preambles do not vary with the data. -
Page 81: External Filter Components
CS42528 12.1 External Filter Components 12.1.1 General The PLL behavior is affected by the external filter component values in the Typical Connection Diagrams. Figure 5 show the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. The external PLL component values listed in Table 21 have a high corner frequency jitter atten- uation curve, take a short time to lock, and offer good output jitter performance. -
Page 82: Capacitor Selection
CS42528 12.1.3 Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. -
Page 83: Appendix D: External Aes3/Spdif/Iec60958 Receiver Components
CS42528 13. APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 13.1 AES3 Receiver External Components The CS42528 AES3 receiver is designed to accept only consumer-standard interfaces. The standards call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector is an RCA phono socket. -
Page 84: Appendix E: Adc Filter Plots
CS42528 14. APPENDIX E: ADC FILTER PLOTS -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 33. Single Speed Mode Stopband Rejection Figure 34. -
Page 85: Figure 39. Double Speed Mode Transition Band (Detail)
CS42528 ‘ 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 39. Double Speed Mode Transition Band (Detail) Figure 40. -
Page 86: Appendix F: Dac Filter Plots
CS42528 15. APPENDIX F: DAC FILTER PLOTS 0.42 0.44 0.46 0.48 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 45. Single Speed (fast) Stopband Rejection Figure 46. Single Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02... -
Page 87: Figure 51. Single Speed (Slow) Transition Band (Detail)
CS42528 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.05 0.15 0.25 0.35 0.45 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 51. Single Speed (slow) Transition Band (detail) Figure 52. Single Speed (slow) Passband Ripple 0.42 0.44 0.46... -
Page 88: Figure 57. Double Speed (Slow) Stopband Rejection
CS42528 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 57. Double Speed (slow) Stopband Rejection Figure 58. Double Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 0.05 0.15 0.25 0.35... -
Page 89: Figure 63. Quad Speed (Fast) Transition Band (Detail)
CS42528 0.15 0.05 0.05 0.15 0.05 0.15 0.25 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 63. Quad Speed (fast) Transition Band (detail) Figure 64. Quad Speed (fast) Passband Ripple Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 65. -
Page 90: Table 22. Revision History
CS42528 Table 22. Revision History Release Date Changes December 2002 Advance Release August 2003 Preliminary Release August 2003 – Added Revision History table. – Updated registers 6.7.4 and 6.7.5 on page 54. March 2004 Corrected error in document title. July 2004 Add lead free part numbers January 2005 –... - Page 91 ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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