Electrostatic Discharge (Esd) Protection Circuitry - Cirrus Logic CS42L42 Manual

1.4 Electrostatic Discharge (ESD) Protection Circuitry

ESD-sensitive device. The CS42L42 is manufactured on a CMOS process. Therefore, it is generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while
handling and storing this device. This device is qualified to current JEDEC ESD standards.
Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the
substrate (GNDA) and the interrelations between some domains. Note that this figure represents the structure for the
internal protection devices and that additional protections can be implemented as part of the integration into the board.
GNDL
*
Substrate
(GNDA)
____________________
VL/GNDA Domain
Note: The asterisks indicate the pads with which the individual
pins from the corresponding domains are associated. These
pins are listed in
Table 1-2 shows the individual ESD domains and lists the pins associated with each domain.
ESD Signal Name (CSP/QFN)
Domain (See * in Topology Figures for Pad)
AD0
VL/
AD1
GNDA 1
ASP_LRCK/FSYNC
GNDL
SCL
SDA
ASP_SDOUT
SPDIF_TX
SWIRE_SEL
ASP_SCLK/SWIRE_CLK
SWIRE_SD/ASP_SDIN
VD_FILT
VL
VD_FILT
VD_FILT/
GNDD
GNDA
TSTI
VA/ FILT+
GNDA
GNDA
VA
DS1083F2
VD_FILT
VL
GNDD GNDA
_______________ ____________________
VD_FILT/GNDA VA/GNDA Domain
Domain
Table 1-2.
Figure 1-3. Composite ESD Topology
1.4 Electrostatic Discharge (ESD) Protection Circuitry
VA VCP
GNDHS
*
__________
VCP/GNDA
Domain
Table 1-2. ESD Domains
–VCP_FILT/+VCP_FILT Domain
VP/GNDA Domain
VP
*
*
*
VP/–VCP_FILT Domain
Topology
GNDL
Substrate
(GNDA)
VL
GNDD
Substrate
(GNDA)
GNDA
Substrate
(GNDA)
CS42L42
+VCP_FILT
GNDCP
Substrate
(GNDA)
–VCP_FILT
VL VD_FILT
*
VD_FILT
*
VA
*
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