Cirrus Logic CS42L42 Manual page 90

Example 5-1. Power-Up Sequence (Cont.)
S T
TEP ASK
4.8 Configure the ASP
clock.
4.9 Configure the ASP
frame.
4.10Configure the
AudioPort interface.
4.11Configure serial port
receive channel
positions.
4.12Set receive sample
rate.
4.13Configure the ASP
receiver.
4.14Configure Channel 1
size to 24 bits per
sample.
4.15Configure location of
the Channel 1 MSB
with respect to SOF.
4.16Configure location of
the Channel 1 LSB
with respect to SOF.
4.17Configure the SRC
sample rate
detection.
4.18Configure Channel 2
size to 24 bits per
sample.
4.19Configure location of
the Channel 2 MSB
with respect to SOF.
4.20Configure location of
the Channel 2 LSB
with respect to SOF.
4.21Disable the SRC
bypass.
DS1083F2
R /B F
EGISTER IT
ASP Clock Configuration 1. 0x1207
Reserved
ASP_SCLK_EN
ASP_HYBRID_MODE
ASP_SCPOL_IN_ADC
ASP_SCPOL_IN_DAC
ASP_LCPOL_OUT
ASP_LCPOL_IN
ASP Frame Configuration. 0x1208
Reserved
ASP_STP
ASP_5050
ASP_FSD
Serial Port Receive Isochronous Control. 0x2502
Reserved
SP_RX_RSYNC
Reserved
SP_RX_ISOC_MODE
Serial Port Receive Channel Select. 0x2501
Reserved
SP_RX_CHB_SEL
SP_RX_CHA_SEL
Serial Port Receive Sample Rate. 0x2503
Reserved
SP_RX_FS
ASP Receive Enable. 0x2A01
ASP_RX1_CH_EN
ASP_RX0_CHF_EN
ASP_RX1_2FS
ASP_RX0_2FS
ASP Receive DAI0 Channel 1 Phase and Resolution.
0x2A02
Reserved
ASP_RX0_CH1_AP
Reserved
ASP_RX_CH1_RES
ASP Receive DAI0 Channel 1 Bit Start MSB. 0x2A03
Reserved
ASP_RX0_CH1_BIT_ST_MSB
ASP Receive DAI0 Channel 1 Bit Start LSB. 0x2A04
ASP_RX0_CH1_BIT_ST_LSB
SRC Input Sample Rate. 0x2601
Reserved
SRC_SDIN_FS
ASP Receive DAI0 Channel 2 Phase and Resolution.
0x2A05
Reserved
ASP_RX0_CH2_AP
Reserved
ASP_RX_CH2_RES
ASP Receive DAI0 Channel 2 Bit Start MSB. 0x2A06
Reserved
ASP_RX0_CH2_BIT_ST_MSB
ASP Receive DAI0 Channel 2 Bit Start LSB. 0x2A07
ASP_RX0_CH2_BIT_ST_LSB
Serial Port SRC Control. 0x1007
Reserved
EQ_BYPASS
I2C_DRIVE
ASP_DRIVE
SRC_BYPASS_DAC
SRC_BYPASS_ADC
V
IELDS ALUE
0x00
00
0
0
0
0
0
0
0x10
000
1
0
000
0x04
0
0
00 01
00
0x04
0000
01
00
0x8C
100
0 1100
0x00
00
00 00
0
0
0x02
0
0
0000
10
0x00
0000 000
0
0x00
0000 0000 ASP transmit bit start LSB = 0.
0x20
0010
0000
0x02
0
0
00 00
10
0x00
0000 000
0
0x18
0001 1000 ASP transmit bit start LSB = 24.
0x10
000
1
0
0
0
0
5.1 Power-Up Sequence
D
ESCRIPTION
—
ASP SCLK disabled.
LRCK is an input from an external source.
SCLK input drive polarity for ADC is normal.
SCLK input drive polarity for DAC is normal.
LRCK output drive polarity is normal.
LRCK input polarity (pad to logic) is normal.
—
Frame begins when LRCK transitions low to high
LRCK duty cycle per FSYNC_PULSE_WIDTH_LB/UB
Zero SCLK frame start delay
—
Serial port default receive synchronization.
—
Serial port receive in native mode.
—
SP RX Channel B position is 1.
SP RX Channel A position is 0.
—
SP receive sample rate = 48 kHz.
RX1 buffer is disabled.
RX0 buffer is disabled.
ASP DAI1 is standard sample rate.
ASP DAI0 is standard sample rate.
—
In 50/50 mode, channel data valid if LRCK is low.
—
Size is 24 bits per sample.
—
ASP receive bit start MSB = 0.
—
ASP sample rate is autodetected.
—
In 50/50 mode, channel data valid if LRCK is low.
—
Size is 24 bits per sample.
—
ASP receive bit start MSB = 0.
—
Bypass equalizer
I 2 C output drive strength normal
ASP output drive strength normal
SRC not bypassed for DAC path
SRC not bypassed for ADC path
CS42L42
90