Slave Data Port 1-3, 15 Registers - Cirrus Logic CS42L42 Manual

Address Function
0x00D0 Memory Access
Status
p. 122
0x00D1 Memory Access
Control
p. 122
0x00D2 Memory Access
Timeout
p. 123
0x00D3 Reserved
0x00D4 Memory Read Last
Address 0
p. 123
0x00D5 Memory Read Last
Address 1
p. 123
0x00D6–0x00D7 Reserved
0x00D8 Memory Read
Data 0
p. 123
0x00D9–0x00FF Reserved
6.3 Slave Data Port 1–3, 15 Registers
Port 1 base address = 0x0100; Port 2 base address = 0x0200; Port 3 base address = 0x0300; Port 15 base address = 0x0F00
Address
Function
+0x00 DPn Interrupt Status
p. 123
+0x01 DPn Interrupt Mask
p. 124
+0x02 DPn Port Control
p. 124
+0x03 DPn Block Control 1
p. 124
+0x03–+0x04 Reserved
+0x04 DPn Prepare Status
p. 125
+0x05 DPn Prepare
Control
p. 125
+0x06–+0x1F Reserved
+0x20 DPn Channel
Enable
p. 125
+0x21 Reserved
+022 DPn Sample
Control 1
p. 125
+0x23 DPn Sample
Control 2
p. 126
DS1083F2
Slave Control Port Registers
7 6 5
—
—
0 0 0
0 0 0
—
—
0 0 0
0 0 0
0 0 0
0 0 0
Slave Data Port 1–3, 15 Registers
7 6 5
0 0 0
0 0 0
—
—
0 0 0
—
—
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
6.3 Slave Data Port 1–3, 15 Registers
4 3
LAST_LATE
0 0
—
—
0 0
TIMEOUT_
DISABLE
0 0
—
MEM_READ_LAST_ADDR[7:0]
R/O
0 0
MEM_READ_LAST_ADDR[15:8]
R/O
0 0
—
MEM_READ_DATA[7:0]
R/O
0 0
—
4 3
—
—
0 0
—
—
0 0
INVERT_BANK PORT_DATA_MODE
0 0
WORD_LENGTH
R/W
0 0
—
—
R/O
0 0
—
R/W
0 0
—
—
R/W
0 0
—
SAMPLE_INTERVAL_LOW
R/W
0 0
SAMPLE_INTERVAL_HIGH
R/W
0 0
CS42L42
2 1
CMD_IN_ CMD_DONE RDATA_RDY
PROGRESS
R/O
0 0
LATE_RESP
R/W
0 0
TIMEOUT_CTRL
R/W
0 0
0 0
0 0
0 0
2 1
STAT_PORT_ STAT_TEST_
READY
R/W1C
0 0
PORT_ TEST_FAIL_M
READY_M
R/W
0 0
—
R/W
0 0
0 0
NOT_
FINISHED_ FINISHED_
CHANNEL2 CHANNEL1
0 0
PREPARE_ PREPARE_
CHANNEL2 CHANNEL1
0 0
CHANNEL_ CHANNEL_EN1
EN2
0 0
0 0
0 0
0
0
R/W
1
0
0
0
0
0
FAIL
0
0
0
0
NOT_
0
0
0
1
0
105