Cirrus Logic CS42L42 Manual page 74

SPDIF_LRCK_SRC_SEL(see
Configuration bits mentioned above must be programmed before powering up the DAI ports and the S/PDIF transmit port.
4.10.2 S/PDIF, Headphone, and ADC Simultaneous Clocking Configuration
S/PDIF transmission requires an SCLK of 128 x Fs supplied either from the ASP_SCLK/SWIRE_CLK input pin or from the
internal fractional-N PLL. When operating the S/PDIF transmitter with no other data converters enabled, the source of the
transmission clock is freely chosen between the input pin and the PLL. When simultaneous operation of the data
converters and the S/PDIF transmitter is desired, a 128 x Fs clock must be supplied from the ASP_SCLK/SWIRE_CLK
input. Table 4-19 describes the supported clocks for simultaneous operation.
Table 4-19. S/PDIF, Headphone, and ADC Simultaneous Clocking Support
LRCK (kHz) S/PDIF HP (Isochronous)
48 48 8, 11.025, 12, 16, 22.05,
24, 32, 44.1
48 2 x 48 1 16, 22.05, 24, 32, 44.1,
48, 88.2
96 96
96 2 x 96 1 32, 44.1, 48, 88.2, 96
192 192
Fs Fs Fs (Native)
2 x Fs 1
1.ASP_RX1_2FS = 1.
For proper S/PDIF signal timing, the divide factor, selected with
the following formula:
Divide factor = MCLK
(where Fs is the data rate to the S/PDIF block and not the external LRCK)
For example, for an S/PDIF output Fs of 192 kHz, 128 X 192 kHz = 24.576 MHz. If ASP_SCLK is 24.576 MHz, the divide
factor must be 1 (SPDIF_CLK_DIV = 000).
Note: Due to SPDIF_CLK_DIV being limited to 1, 2, 3, 4, and 8, a 32-kHz S/PDIF Fs is not supported with a 24.576-MHz
ASP_SCLK/SWIRE_CLK.
4.10.3 Interface Formats
This section describes the frame and subframe formats, channel coding, and Keep-Alive Mode.
4.10.3.1 Frame Format
A frame (see Fig. 4-39) is uniquely composed of two subframes (see
transmitted by time multiplexing in consecutive subframes. The first subframe normally starts with Preamble M; however,
to identify the start of the block structure used to organize the channel status information, the preamble changes to B once
every 192 frames. The second subframe always begins with Preamble W.
The frame format is the same for one- and two-channel operations. Data is carried in the first subframe and may be
duplicated in the second. If the second subframe does not carry duplicate data, the validity flag (Time Slot 28) must be set
to Logic 1.
DS1083F2
p. 136) selects the S/PDIF LRCK source.
HSIN (Isochronous)
8,11.025, 12, 16, 22.05, 24,
32, 44.1
16, 22.05, 24, 32, 44.1, 48 12.288, 24.576
32, 44.1, 48
Fs (Native)
/(128 x Fs)
INT
SPDIF_LRCK_CPOL
SCLK (MHz)
6.144, 12.288, 12.288, 24.576
24.576
12.288, 24.576
24.576 24.576
128xFs 11.2896, 12.288, 22.8796, 24.576 MHz
SPDIF_CLK_DIV (see p.
Fig. 4-40). Samples taken from both channels are
CS42L42
4.10 S/PDIF Tx Port
(see p. 137) sets polarity.
PLL Output (MHz)
136), must be chosen by using
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