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104 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-90 dB THD+N
Up to 192 kHz Sampling Rates
Single-Ended Analog Architecture
Volume Control with Soft Ramp
–
0.5 dB Step Size
–
Zero Crossing, Click-Free Transitions
®
Popguard
Technology
–
Minimizes the Effects of Output Transients
Filtered Line-Level Outputs
Selectable Serial Audio Interface Formats
–
Left-Justified up to 24-bit
–
I²S up to 24-bit
–
Right-Justified 16-, 18-, 20-, and 24-bit
Selectable 50/15 µs De-Emphasis
1.8 V to 5 V
Serial
Audio
Input
Serial
Audio
Output
2
I
C Control
Data
Reset
http://www.cirrus.com
3.3 V to 5 V
Volume
Interpolation
Control
Filter
Volume
Interpolation
Control
Filter
IEC60958-3 Transmitter
High Pass
Low-Latency
Filter
Anti-Alias Filter
High Pass
Low-Latency
Filter
Anti-Alias Filter
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
A/D Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 2:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
–
± 12 dB Gain, 0.5 dB Step Size
–
Zero Crossing, Click-Free Transitions
Pseudo-Differential Stereo Line Inputs
Stereo Microphone Inputs
–
+32 dB Gain Stage
–
Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
–
Left-Justified up to 24-bit
–
I²S up to 24-bit
High-Pass Filter or DC Offset Calibration
3.3 V to 5 V
Multibit
Switched Capacitor
Modulator
DAC and Filter
Multibit
Switched Capacitor
Modulator
DAC and Filter
Internal Voltage
Reference
Multibit
PGA
Oversampling
ADC
Multibit
Oversampling
ADC
CS4265
Left DAC Output
Mute
Mute Control
Control
Right DAC Output
Transmitter Output
Microphone Bias
Mic Bias
+32 dB
Mic Input
1 & 2
MUX
+32 dB
Stereo
PGA
Line Input
AUG '12
DS657F3
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Table of Contents
Related Manuals for Cirrus Logic CS4265
Summary of Contents for Cirrus Logic CS4265
- Page 1 High Pass Low-Latency +32 dB Oversampling Filter Anti-Alias Filter Mic Input 1 & 2 Reset +32 dB Multibit Stereo High Pass Low-Latency Oversampling Line Input Filter Anti-Alias Filter Copyright Cirrus Logic, Inc. 2012 AUG '12 (All Rights Reserved) DS657F3 http://www.cirrus.com...
- Page 2 CS4265 and other devices operating over a wide range of logic levels. The CS4265 is available in a 32-pin QFN package for both Commercial (-10° to +70° C) and Automotive (-40° to +105° C) grade. The CDB4265 is also available for device evaluation and implementation suggestions.
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Page 3: Table Of Contents
CS4265 TABLE OF CONTENTS 1. PIN DESCRIPTIONS .......................... 7 2. CHARACTERISTICS AND SPECIFICATIONS ..................9 SPECIFIED OPERATING CONDITIONS ..................... 9 ABSOLUTE MAXIMUM RATINGS ....................... 9 DAC ANALOG CHARACTERISTICS ....................10 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ......11 ADC ANALOG CHARACTERISTICS .................... - Page 4 CS4265 6.3.1 DAC Digital Interface Format (Bits 5:4) ................. 37 6.3.2 Mute DAC (Bit 2) ........................37 6.3.3 De-Emphasis Control (Bit 1) ....................38 6.4 ADC Control - Address 04h ......................38 6.4.1 Functional Mode (Bits 7:6) ....................38 6.4.2 ADC Digital Interface Format (Bit 4) ..................38 6.4.3 Mute ADC (Bit 2) ........................
- Page 5 CS4265 11.1.1 Accessing the E Buffer ......................54 11.2 Serial Copy Management System (SCMS) .................. 54 11.3 Channel Status Data E Buffer Access ..................54 11.3.1 One-Byte Mode ........................55 11.3.2 Two-Byte Mode ........................55 12. PACKAGE DIMENSIONS ........................56 13.
- Page 6 CS4265 Figure 42.Consumer Output Circuit (VD = 5 V) ..................52 Figure 43.TTL/CMOS Output Circuit ......................52 Figure 44.Channel Status Data Buffer Structure ..................53 Figure 45.Flowchart for Writing the E Buffer ..................... 54 LIST OF TABLES Table 1. Speed Modes ..........................24 Table 2.
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Page 7: Pin Descriptions
CS4265 1. PIN DESCRIPTIONS SDIN2 TXSDIN RESET MUTEC Thermal Pad AOUTB AGND AOUTA AINA AGND Top-Down (Through Package) View 32-Pin QFN Package AINB Pin Name Pin Description Serial Control Data (Input/Output) - Bidirectional data line for the I²C control port. - Page 8 CS4265 Analog Power (Input) - Positive power for the internal analog section. AGND Analog Ground (Input) - Ground reference for the internal analog section. AOUTA 19, 20 Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Characteris- AOUTB tics specification table.
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Page 9: Characteristics And Specifications
CS4265 2. CHARACTERISTICS AND SPECIFICATIONS SPECIFIED OPERATING CONDITIONS AGND = DGND = 0 V; All voltages with respect to ground. Parameters Symbol Units DC Power Supplies: Analog 3.13 5.25 Digital 3.13 (Note 1) Logic - Serial Port 1.71 5.25 Logic - Control Port 1.71... -
Page 10: Dac Analog Characteristics
CS4265 DAC ANALOG CHARACTERISTICS Test Conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T = -10°... -
Page 11: Dac Combined Interpolation & On-Chip Analog Filter Response
CS4265 6. Guaranteed by design. See Figure 2. R and C reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp’s stability. C affects the dominant pole of the internal output amp; increasing C beyond 100 pF can cause the internal op-amp to become unstable. -
Page 12: Figure 1.Dac Output Test Load
CS4265 3.3 µF AOUTx Safe Operating Region AGND Resistive Load -- R (k ) Figure 1. DAC Output Test Load Figure 2. Maximum DAC Loading DS657F3... -
Page 13: Adc Analog Characteristics
CS4265 ADC ANALOG CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VA = 3.13 V to 5.25 V; VD = 3.13 V to 5.25 V or VA + 0.25 V, whichever is less; VLS = VLC = 1.71 V to 5.25 V; T = -10°... - Page 14 CS4265 DC Accuracy Gain Error Gain Drift ppm/°C Line-Level Input Characteristics Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA Input Impedance (Note 11) 6.12 7.48 k Maximum Interchannel Input Impedance Mismatch Line-Level and Microphone-Level Inputs Commercial Grade Parameter Symbol Unit...
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Page 15: Adc Analog Characteristics
CS4265 ADC ANALOG CHARACTERISTICS (Continued) Microphone-Level Inputs Parameter Symbol Unit Dynamic Performance for VA = 4.75 V to 5.25 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise... -
Page 16: Adc Digital Filter Characteristics
CS4265 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Notes 15, 17) Symbol Unit Single-Speed Mode Passband (-0.1 dB) 0.4896 Passband Ripple 0.035 Stopband 0.5688 Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) 12/Fs Double-Speed Mode Passband (-0.1 dB) 0.4896 Passband Ripple 0.025... -
Page 17: Dc Electrical Characteristics
CS4265 DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode. Parameter Symbol Unit Power Supply Current VA = 5 V (Normal Operation) VA = 3.3 V VD, VLS, VLC = 5 V VD, VLS, VLC = 3.3 V... -
Page 18: Digital Interface Characteristics
CS4265 DIGITAL INTERFACE CHARACTERISTICS Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 1.71 V to 5.25 V. (Note 21) Parameters Symbol Units High-Level Input Voltage VL = 1.71 V Serial Port 0.8xVLS Control Port 0.8xVLC... -
Page 19: Switching Characteristics - Serial Audio Port
CS4265 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VL, C = 20 pF. (Note 23) Parameter Symbol Unit Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode MCLK Specifications MCLK Frequency 1.024... -
Page 20: Figure 3.Master Mode Serial Audio Port Timing
CS4265 LRCK O utput SCLK O utput SDO UT sdis sdih SDIN Figure 3. Master Mode Serial Audio Port Timing LRCK Input sclkh sclkl SCLK Input sclkw SDOUT sdis sdih SDIN Figure 4. Slave Mode Serial Audio Port Timing DS657F3... -
Page 21: Figure 5.Format 0, Left-Justified Up To 24-Bit Data
CS4265 Channel B - Right Channel A - Left LRCK SCLK SDATA +5 +4 +3 +2 +1 +5 +4 +2 +1 Figure 5. Format 0, Left-Justified up to 24-Bit Data Channel A - Left Channel B - Right LRCK SCLK... -
Page 22: Switching Characteristics - I²C Control Port
CS4265 SWITCHING CHARACTERISTICS - I²C CONTROL PORT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, C = 30 pF. Parameter Symbol Unit SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions µs... -
Page 23: Typical Connection Diagram
SCLK This circuitry is intended for applications where the CS4265 connects directly to an unbalanced output of the design . For internal LRCK routing applications please see the DAC Analog Output Characteristics section for loading limitations. -
Page 24: Applications
3. The desired register settings can be loaded while the PDN bit remains set. 4. Clear the PDN bit to initiate the power-up sequence. System Clocking The CS4265 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed modes as shown in Table... -
Page 25: Master Mode
High-Pass Filter and DC Offset Calibration When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven into the A/D converter. The CS4265 includes a high-pass filter after the decimator to remove any DC offset... - Page 26 This feature makes it possible to perform a system DC offset cal- ibration by: 1. Running the CS4265 with the high-pass filter enabled until the filter settles. See the ADC Digital Filter Characteristics section for filter settling time.
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Page 27: Analog Input Multiplexer, Pga, And Mic Gain
Any unused analog input pairs should be left unconnected. 4.5.1 Pseudo-Differential Input The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a pseudo-differential reference signal. This feature allows for common mode noise rejection with single- ended signals. -
Page 28: Output Connections
48”. The recommended external analog circuitry is shown in the Typical Connection Diagram. The CS4265 DAC does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response is dependent on the external analog circuitry. -
Page 29: Dac Serial Data Input Multiplexer
Internal Digital Loopback The CS4265 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (See “Signal... -
Page 30: Mute Control
The transmitter is clocked from the clock input pin MCLK. The channel status (C) bits in the transmitted data stream are taken from storage areas within the CS4265. The user can manually access the internal storage of the CS4265 to configure the transmitted channel sta- tus data. -
Page 31: Mono Mode Operation
SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4265 after a Start condition consists of a 7-bit chip address field and an R/W bit (high for a read, low for a write). -
Page 32: Status Reporting
Send acknowledge bit. Send stop condition. 4.14 Status Reporting The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status register, as listed in the status register descriptions. See “Status - Address 0Dh” on page 43. Each source may be masked off through mask register bits. -
Page 33: Reset
CS4265s in the system. If only one master clock source is needed, one solution is to place one CS4265 in Master Mode, and slave all of the other CS4265s to the one master. -
Page 34: Register Quick Reference
CS4265 5. REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr Function 01h Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0 02h Power Control Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC PDN_DAC 03h DAC Control 1... - Page 35 CS4265 Addr Function 11h Transmitter Reserved EFTCI Reserved Reserved Reserved Reserved Reserved Control 1 12h Transmitter Tx_DIF1 Tx_DIF0 TxOff TxMute MMTCS MMTLR Control 2 13h - C-Data Buffer DS657F3...
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Page 36: Register Description
CS4265 6. REGISTER DESCRIPTION Chip ID - Register 01h PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0 Function: This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1101b (0Dh), and the remaining bits (3 through 0) indicate the device revision as shown in Table 5 below. -
Page 37: Power-Down Dac (Bit 1)
CS4265 6.2.4 Power-Down DAC (Bit 1) Function: The DAC pair will remain in a reset state whenever this bit is set. 6.2.5 Power-Down Device (Bit 0) Function: The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation can occur. -
Page 38: De-Emphasis Control (Bit 1)
CS4265 6.3.3 De-Emphasis Control (Bit 1) Function: The standard 50/15 s digital de-emphasis filter response, Figure 17, may be implemented for a sample rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 8. NOTE: De-emphasis is available only in Single-Speed Mode. -
Page 39: Mute Adc (Bit 2)
CS4265 ADC_DIF Description Format Figure Left-Justified, up to 24-bit data (default) I²S, up to 24-bit data Table 10. ADC Digital Interface Formats 6.4.3 Mute ADC (Bit 2) Function: When this bit is set, the serial audio output of the both ADC channels is muted. -
Page 40: Signal Selection - Address 06H
CS4265 Signal Selection - Address 06h SDINSel Reserved Reserved Reserved Reserved Reserved LOOP Reserved 6.6.1 DAC SDIN Source (Bit 7) Function: This bit is used to select the serial audio data source for the DAC as shown in Table SDINSel Setting... -
Page 41: Adc Input Control - Address 09H
CS4265 ADC Input Control - Address 09h Reserved Reserved Reserved PGASoft PGAZero Reserved Reserved Select 6.9.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) Function: Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. -
Page 42: Dac Channel B Volume Control - Address 0Bh
CS4265 6.11 DAC Channel B Volume Control - Address 0Bh Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0 6.11.1 Volume Control (Bits 7:0) Function: The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB. -
Page 43: Invert Dac Output (Bit 5)
CS4265 ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon- itored and implemented for each channel. See Table DACSoft DACZeroCross Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default) Table 17. -
Page 44: Status Mask - Address 0Eh
CS4265 6.14 Status Mask - Address 0Eh Reserved Reserved Reserved EFTCM ClkErrM Reserved ADCOvflM ADCUndrflM Function: The bits of this register serve as a mask for the Status sources found in the register “Status - Address 0Dh” on page 43. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. -
Page 45: Transmitter Control 2 - Address 12H
CS4265 6.18 Transmitter Control 2 - Address 12h Tx_DIF1 Tx_DIF0 TxOff TxMute MMTCS MMTLR 6.18.1 Transmitter Digital Interface Format (Bits 7:6) Function: The required relationship between LRCK, SCLK and SDIN for the transmitter is defined by the Transmitter Digital Interface Format and the options are detailed in... -
Page 46: Mono Mode Channel Selection (Bit 0)
CS4265 6.18.7 Mono Mode Channel Selection (Bit 0) Function: When this bit is cleared, channel A input data will be transmitted in both channel A and B subframes in mono mode. When this bit is set, channel B input data will be transmitted in both channel A and B sub- frames in Mono Mode. -
Page 47: Parameter Definitions
CS4265 7. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. -
Page 48: Dac Filter Plots
CS4265 8. DAC FILTER PLOTS Figure 18. DAC Single-Speed Stopband Rejection Figure 19. DAC Single-Speed Transition Band 0.05 -0.05 -0. 1 -0.15 -0. 2 -0.25 0.05 0.15 0.25 0.35 0.45 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.5 5... -
Page 49: Figure 24.Dac Double-Speed Transition Band
CS4265 -0. 1 - 10 -0. 2 0.05 0.15 0.25 0.35 0.45 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 24. DAC Double-Speed Transition Band Figure 25. DAC Double-Speed Passband Ripple -100 0.35... -
Page 50: Adc Filter Plots
CS4265 9. ADC FILTER PLOTS -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 30. ADC Single-Speed Stopband Rejection Figure 31. -
Page 51: Figure 36.Adc Double-Speed Transition Band (Detail)
CS4265 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (norm alized to Fs) Frequency (norm alized to Fs) Figure 36. -
Page 52: External Iec60958-3 Transmitter Components
CS4265 10.EXTERNAL IEC60958-3 TRANSMITTER COMPONENTS This section details the external components required to interface the IEC60958-3 transmitter to cables and fiber- optic components. 10.1 IEC60958-3 Transmitter External Components The IEC60958-3 specifications call for an unbalanced drive circuit with an output impedance of 75 ... -
Page 53: Channel Status Buffer Management
IEC60958-3 Channel Status (C) Bit Management The CS4265 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384 bits). The user may read from, or write to, these RAM buffers through the control port. -
Page 54: Accessing The E Buffer
E buffer. The E buffer is only accessible when an MCLK signal is applied to the CS4265 and the device is out of the power-down state (the PDN bit in register 02h is cleared). If either of these conditions is not met, the values stored in the E buffer will not change when written via the control port. -
Page 55: One-Byte Mode
E buffer. In this mode, a read will cause the CS4265 to output two bytes from its control port. The first byte out rep- resents the A channel status data, and the second byte represents the B channel status data. Writing is similar, in that two bytes must now be input to the CS4265's control port. -
Page 56: Package Dimensions
CS4265 12.PACKAGE DIMENSIONS 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING Pin #1 Corner Pin #1 Corner Bottom View Top View Side View INCHES MILLIMETERS NOTE 0.0394 1.00 0.0000 0.0020 0.00 0.05 0.0071 0.0091 0.0110 0.18 0.23 0.28 0.1969 BSC 5.00 BSC... -
Page 57: Ordering Information
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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