Soundwire Control Port 0 Registers - Cirrus Logic CS42L42 Manual

7.1 SoundWire Control Port 0 Registers

7.1.1 SCP Interrupt Status 1
7
PORT3_
—
CASCADE
Default 0
Bits Name
7 — Reserved
6:4 PORTx_ Port x cascade. Indicates whether at least one unmasked interrupt condition is set in the corresponding DPn interrupt status
CASCADE register. The interrupt must be cleared at its source in the DPn interrupt status register.
0 (Default) No unmasked interrupt conditions in the DPn interrupt status register
1 At least one unmasked interrupt condition in DPn interrupt status register
3 — Reserved
General interrupt cascade. Indicates whether at least one unmasked interrupt condition is set in the general interrupt status
2 GEN_INT_
CASCADE registers 1 and 2. The interrupt must be cleared at its source in the general interrupt status registers.
1 STAT_ Bus clash status. Indicates whether an interrupt is pending due to detection of a bus clash on the SoundWire bus. If the
BUS_ corresponding mask bit is set, this event can generate an interrupt. Writing a 1 to the bit clears it and its associated interrupt.
CLASH A sync loss reset does not clear the bit.
0 (Default) No bus collision detected.
1 Bus collision detected
0 STAT_ Parity status. Indicates whether a parity error is detected on the SoundWire bus. If the corresponding mask bit is set, the event
PARITY can generate an interrupt. Writing a 1 to the bit clears it and its associated interrupt. A sync loss reset does not clear the bit.
0 (Default) No parity error detected.
1 Parity error detected
7.1.2 SCP Interrupt Mask 1
7
Default
0
Bits Name
7:2 — Reserved
1 MASK_ Bus clash mask. Determines whether a bus collision event generates an interrupt
BUS_
0 (Default) A bus collision does not generate an interrupt.
CLASH
1 A bus collision generates an interrupt.
0 MASK_ Bus parity error mask. Determines whether a parity error event generates an interrupt
PARITY
0 (Default) A parity error does not generate an interrupt.
1 A parity error generates an interrupt.
7.1.3 SCP Control
7
FORCE_RESET CURRENT_BANK
W/O
Default
0
Bits Name
7 FORCE_ Force reset (write only). Used to trigger an internal reset. See
RESET
0 (Default) No action
1 Force internal reset.
6 CURRENT_ Current bank. Identifies the current register bank.
BANK
0 (Default) current register bank is Bank 0
1 Current register bank is Bank 1
5:2 — Reserved
DS1083F2
6 5
PORT2_
CASCADE
R/O
0 0
6 5
—
—
0 0
6 5 4
R/O
0 0 0
4 3
PORT1_
—
CASCADE
0 0
Description
4 3
0 0
Description
3 2
— CLOCK_STOP_NOW CLOCK_STOP_NOT_FINISHED
R/O
0 0
Description
Section 4.17
7.1 SoundWire Control Port 0 Registers
Address Base + 0x40
2 1
GEN_INT_ STAT_BUS_
CASCADE CLASH
R/W1C
0 0
Address Base + 0x41
2 1
MASK_BUS_CLASH MASK_PARITY
R/W
0 0
Address Base + 0x44
1
W/O
0
for details.
CS42L42
0
STAT_PARITY
R/W1C
0
0
R/W
0
0
R/O
1
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