Cirrus Logic CS42L42 Manual page 165

7.22.2 ASP Receive DAI0 Channel 1 Phase and Resolution
R/W
7
— ASP_RX0_CH1_AP
Default
0
Bits Name
7 — Reserved
6 ASP_RX0_ ASP receive DAI0 active phase. Valid only in 50/50 Mode (ASP_5050 = 1 and ASP_RXx_2FS = 0).
CH1_AP
0 (Default) Low. In 50/50 Mode, channel data is valid if LRCK/FSYNC is low.
1 High. In 50/50 Mode, channel data is valid when LRCK/FSYNC is high.
5:2 — Reserved
1:0 ASP_RX0_ ASP Receive DAI0 channel bit width. Sets output resolution of the ASP receive DAI0 channel x samples.
CH1_RES 00 8 bits per sample (only for isochronous NFS and native modes)
01 16 bits per sample
7.22.3 ASP Receive DAI0 Channel 1 Bit Start MSB
R/W
7
Default 0
Bits Name
7:1 — Reserved
0 ASP_RX0_CH1_ ASP receive DAI0 Channel 1 bit start MSB. Configures the MSB location of the channel with respect to SOF (LRCK
BIT_ST_MSB edge + phase lag)
7.22.4 ASP Receive DAI0 Channel 1 Bit Start LSB
R/W
7
Default
0
Bits Name
7:0 ASP_RX0_CH1_ ASP receive DAI0 Channel 1 bit start LSB. Configures the LSB location of the channel with respect to SOF (LRCK
BIT_ST_LSB edge + phase lag)
7.22.5 ASP Receive DAI0 Channel 2 Phase and Resolution
R/W
7
— ASP_RX0_CH2_AP
Default 0
Bits Name
7 — Reserved
6 ASP_RX0_ ASP receive DAI0 active phase. Valid only in 50/50 Mode (ASP_5050 = 1 and ASP_RXx_2FS = 0).
CH2_AP
0 (Default) Low. In 50/50 Mode, channel data is input when LRCK/FSYNC is low.
1 High. In 50/50 Mode, channel data is input when LRCK/FSYNC is high.
5:2 — Reserved
1:0 ASP_RX0_ ASP receive DAI0 channel bit width. Sets the output resolution of the ASP receive DAI0 channel x samples.
CH2_RES 00 8 bits per sample (valid only for isochronous NFS and native mode)
01 16 bits per sample
7.22.6 ASP Receive DAI0 Channel 2 Bit Start MSB
R/W
7
Default
0
Bits Name
7:1 — Reserved
0 ASP_RX0_CH2_ ASP receive DAI0 Channel 2 bit start MSB. Configures the MSB location of the channel with respect to SOF (LRCK
BIT_ST_MSB edge + phase lag).
DS1083F2
6 5
0 0
6 5 4
—
0 0 0
6 5
0 0
6 5
0 0
6 5
—
0 0
4 3
—
0 0
Description
3 2
0 0
Description
4 3
ASP_RX0_CH1_BIT_ST_LSB
0 0
Description
4 3
—
0 0
Description
4 3 2
0 0 0
Description
7.22 Serial Port Receive Registers
2 1
ASP_RX0_CH1_RES
0 1
10 24 bits per sample
11 (Default) 32 bits per sample
1
ASP_RX0_CH1_BIT_ST_MSB
0
2 1
0 0
2 1
ASP_RX0_CH2_RES
0 1
10 24 bits per sample
11 (Default) 32 bits per sample
1
ASP_RX0_CH2_BIT_ST_MSB
0
CS42L42
Address 0x2A02
0
1
Address 0x2A03
0
0
Address 0x2A04
0
0
Address 0x2A05
0
1
Address 0x2A06
0
0
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