Cirrus Logic CS42526 Manual

114 db, 192 khz 6-ch codec with s/pdif receiver

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114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

Features

Six

24-bit D/A, two 24-bit A/D Converters

114 dB DAC / 114 dB ADC Dynamic Range

-100 dB THD+N

System Sampling Rates up to 192 kHz

S/PDIF Receiver Compatible with EIAJ CP1201

and IEC-60958

Recovered S/PDIF Clock or System Clock

Selection

8:2 S/PDIF Input MUX

ADC High-pass Filter for DC Offset Calibration

Expandable ADC Channels and One-line Mode

Support

Digital Output Volume Control with Soft Ramp

Digital +/-15dB Input Gain Adjust for ADC

Differential Analog Architecture

Supports logic levels between 5 V and 1.8 V.

RXP0

RXP1/GPO1

RXP2/GPO2

RXP3/GPO3

RXP4/GPO4

RXP5/GPO5

RXP6/GPO6

RXP7/GPO7

MUTEC

FILT+

REFGND

AGND

AINL+

AINL-

AINR+

AINR-

AOUTA1+

AOUTA1-

AOUTB1+

AOUTB1-

AOUTA2+

AOUTA2-

AOUTB2+

AOUTB2-

AOUTA3+

AOUTA3-

AOUTB3+

AOUTB3-

Preliminary Product Information

Cirrus Logic, Inc.

http://www.cirrus.com

VARX

AGND

TXP

Clock/Data

Recovery

GPO

M UTE

Ref

ADC#1

Digital Filter

ADC#2

Digital Filter

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

General Description

The CS42526 codec provides two analog-to-digital and six dig-

ital-to-analog delta-sigma converters, as well as an integrated

S/PDIF receiver, in a 64-pin LQFP package.

The CS42526 integrated S/PDIF receiver supports up to eight

inputs, clock recovery circuitry and format auto-detection. The

internal stereo ADC is capable of independent channel gain

control for single-ended or differential analog inputs. All six

channels of DAC provide digital volume control and differential

analog outputs. The general purpose outputs may be driven

high or low, or mapped to a variety of DAC mute controls or

ADC overflow indicators.

The CS42526 is ideal for audio systems requiring wide dynam-

ic range, negligible distortion and low noise, such as A/V

receivers, DVD receivers, digital speaker and automotive audio

systems.

ORDERING INFORMATION

CS42526-CQZ

CS42526-DQZ

CDB42528

LPFLT

DGND

DGND VD

C&U Bit

Data Buffer

S/PDIF

Decoder

Form at

Detector

Internal M CLK

DEM

Gain & Clip

ADC

Serial

Data

Gain & Clip

DAC#1

DAC#2

DAC#3

DAC#4

DAC#5

DAC#6

CS42526

-10° to 70° C 64-pin LQFP

-40° to 85° C 64-pin LQFP

Evaluation Board

INT

RST

Control

AD0/CS

Port

AD1/CDIN

SDA/CDOUT

SCL/CCLK

VLC

OM CK

M ult/Div

RM CK

Serial

SAI_LRCK

Audio

SAI_SCLK

Interface

SAI_SDOUT

Port

VLS

ADCIN1

ADCIN2

CX_SDOUT

CX_LRCK

CX_SCLK

CX_SDIN1

CX_SDIN2

CODEC

CX_SDIN3

Serial

Port

Lead Free

JAN '05

DS585PP5

Table of Contents

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Summary of Contents for Cirrus Logic CS42526

Page 1 8:2 S/PDIF Input MUX ADC overflow indicators. ADC High-pass Filter for DC Offset Calibration The CS42526 is ideal for audio systems requiring wide dynam- ic range, negligible distortion and low noise, such as A/V Expandable ADC Channels and One-line Mode...
Page 2: Table Of Contents
CS42526 TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ................ 7 SPECIFIED OPERATING CONDITIONS ................. 7 ABSOLUTE MAXIMUM RATINGS ................... 7 ANALOG INPUT CHARACTERISTICS ..................8 A/D DIGITAL FILTER CHARACTERISTICS................9 ANALOG OUTPUT CHARACTERISTICS ................10 D/A DIGITAL FILTER CHARACTERISTICS................11 SWITCHING CHARACTERISTICS ..................
Page 3 CS42526 5. REGISTER QUICK REFERENCE ..................42 6. REGISTER DESCRIPTION ....................46 6.1 Memory Address Pointer (MAP) ..................46 6.2 Chip I.D. and Revision Register (address 01h) (Read Only) ..........46 6.3 Power Control (address 02h).................... 47 6.4 Functional Mode (address 03h)..................48 6.5 Interface Formats (address 04h) ..................
Page 4 Figure 6. Full-Scale Analog Input ....................21 Figure 7. Full-Scale Output ......................22 Figure 8. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ............23 Figure 9. CS42526 Clock Generation ................... 25 Figure 10. I S Serial Audio Formats....................29 Figure 11.
Page 5 CS42526 Figure 43. Quad Speed Mode Transition Band (Detail) ..............84 Figure 44. Quad Speed Mode Passband Ripple................84 Figure 45. Single Speed (fast) Stopband Rejection ..............85 Figure 46. Single Speed (fast) Transition Band ................85 Figure 47. Single Speed (fast) Transition Band (detail) ..............85 Figure 48.
Page 6 CS42526 LIST OF TABLES Table 1. Common OMCK Clock Frequencies ................26 Table 2. Common PLL Output Clock Frequencies................ 26 Table 3. Slave Mode Clock Ratios ....................26 Table 4. Serial Audio Port Channel Allocations................27 Table 5. DAC De-Emphasis ......................49 Table 6.
Page 7: Characteristics And Specifications
Digital 3.13 5.25 Serial Port Interface 5.25 Control Port Interface 5.25 °C Ambient Operating Temperature (power applied) CS42526-CQZ °C CS42526-DQZ ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters Symbol Units DC Power Supply...
Page 8: Analog Input Characteristics
CS42526 ANALOG INPUT CHARACTERISTICS = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.
Page 9: A/D Digital Filter Characteristics
CS42526 A/D DIGITAL FILTER CHARACTERISTICS Parameter Symbol Unit Single Speed Mode (2 to 50 kHz sample rates) Passband (-0.1 dB) (Note 5) 0.47 ±0.035 Passband Ripple Stopband (Note 5) 0.58 Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) 12/Fs ∆t...
Page 10: Analog Output Characteristics
CS42526 ANALOG OUTPUT CHARACTERISTICS = 25° C; VA =VARX= 5 V, VD = 3.3 V, Logic "0" = DGND =AGND = 0 V; Logic "1" = VLS = VLC = 5V; Measurement Bandwidth 10 Hz to 20 kHz unless otherwise specified.;...
Page 11: D/A Digital Filter Characteristics
CS42526 D/A DIGITAL FILTER CHARACTERISTICS Fast Roll-Off Slow Roll-Off Parameter Unit Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz Passband (Note 9) to -0.01 dB corner 0.4535 0.4166 to -3 dB corner 0.4998 0.4998 Frequency Response 10 Hz to 20 kHz -0.01...
Page 12: Switching Characteristics
SAI_LRCK Edge Notes: 12. After powering up the CS42526, RST should be held low after the power supplies and clocks are settled. 13. See Table 1 on page 26 for suggested OMCK frequencies 14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
Page 13: Switching Characteristics - Control Port - I C Format
CS42526 SWITCHING CHARACTERISTICS - CONTROL PORT - I C FORMAT (For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs:...
Page 14: Switching Characteristics - Control Port - Spi Tm Format
CS42526 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (For CQZ, T = -10 to +70° C; For DQZ, T = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C...
Page 15: Dc Electrical Characteristics
CS42526 DC ELECTRICAL CHARACTERISTICS = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode) Parameter Symbol Units Power Supply Current normal operation, VA = VARX = 5 V (Note 22) VD = 5 V VD = 3.3 V µA...
Page 16: Digital Interface Characteristics
CS42526 DIGITAL INTERFACE CHARACTERISTICS (For CQZ, T = +25° C; For DQZ, T = -40 to +85° Parameters (Note 26) Symbol Units 0.7xVLS High-Level Input Voltage Serial Port 0.7xVLC Control Port 0.2xVLS Low-Level Input Voltage Serial Port 0.2xVLC Control Port VLS-1.0...
Page 17: Pin Descriptions
CS42526 2. PIN DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CX_SDIN1 RXP1/G PO 1 CX_SCLK RXP2/G PO 2 CX _LRCK RXP3/G PO 3 RXP4/G PO 4 DGND RXP5/G PO 5...
Page 18 CS42526 Interrupt (Output ) - The CS42526 will generate an interrupt condition as per the Interrupt Mask register. See “Interrupts” on page 40 for more details. Reset ( Input ) - The device enters a low power mode and all internal registers are reset to their default settings when low.
Page 19 ADCs. ADCIN1 External ADC Serial Input ( Input ) - The CS42526 provides for up to two external stereo analog to digital ADCIN2 converter inputs to provide a maximum of six channels on one serial data output line when the CS42526 is placed in One Line mode.
Page 20: Typical Connection Diagram
CS42526 3. TYPICAL CONNECTION DIAGRAM + 3 .3 V to + 5 V + 5 V 0 .0 1 µ F 0 .1 µ F 0 .1 µ F 0 .0 1 µ F 1 0 µ F 1 0 µ F 0 .0 1 µ...
Page 21: Applications
C mode. Figure 5 show the recommended connections for the CS42526. The CS42526 operates in one of three oversampling modes based on the input sample rate. Mode selec- tion is determined by the FM bits in register “Functional Mode (address 03h)” on page 48. Single-Speed mode (SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio.
Page 22: High Pass Filter And Dc Offset Calibration
This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS42526 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time.
Page 23: Digital Volume And Mute Control
(addresses 29h to 2Fh)” on page 69. 4.3.4 ATAPI Specification The CS42526 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 16 on page 60 and Figure 8 for additional infor- mation.
Page 24: S/Pdif Receiver
4.4.1 8:2 S/PDIF Input Multiplexer The CS42526 contains an 8:2 S/PDIF Input Multiplexer to accommodate up to eight channels of input dig- ital audio data. Digital audio data is single-ended and input through the RXP0 and RXP1/GPO1-RXP7/GPO7 pins. Any one of these inputs can be multiplexed to the input of the S/PDIF receiver and to the S/PDIF output pin TXP.
Page 25: Clock Generation
Clock Generation The clock generation for the CS42526 is shown in the figure below. The internal MCLK is derived from the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL lock to the other source input.
Page 26: Omck System Clock Mode
CS42526 4.5.2 OMCK System Clock Mode A special clock switching mode is available that allows the clock that is input through the OMCK pin to be used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock Con- trol (address 06h)”...
Page 27: Digital Interfaces
The Left/Right clock (SAI_LRCK or CX_LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS42526 (master mode), or it may be generated by an external source (slave mode). As described in later sections, particular modes of operation do allow the sample rate, Fs, of the SAI_SP and the CODEC_SP to be different, but must be multiples of each other.
Page 28 CS42526 Serial Inputs / Outputs CX_SDOUT left channel ADC #1 right channel ADC #2 one line mode ADC channels 1,2,3,4,5,6 SAI_SDOUT left channel S/PDIF Left or ADC #1 right channel S/PDIF Right or ADC #2 one line mode ADC channels 1,2,3,4,5,6...
Page 29: Serial Audio Interface Formats
CS42526 4.6.2 Serial Audio Interface Formats The CODEC_SP and SAI_SP digital audio serial ports support 5 formats with varying bit depths from 16 to 24 as shown in Figures 10 to 14. These formats are selected using the configuration bits in the registers, “Functional Mode (address 03h)”...
Page 30: Figure 11. Left Justified Serial Audio Formats
CS42526 CX_LRCK Left Channel Right Channel SAI_LRCK CX_SCLK SAI_SCLK CX_SDINx -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1 CX_SDOUT SAI_SDOUT Left Justified Mode, Data Valid on Rising Edge of SCLK...
Page 31: Figure 13. One Line Mode #1 Serial Audio Format
CS42526 64 clks 64 clks CX_LRCK Left Channel Right Channel SAI_LRCK CX_SCLK SAI_SCLK CX_SDIN1 DAC1 DAC3 DAC5 DAC2 DAC4 DAC6 20 clks 20 clks 20 clks 20 clks 20 clks 20 clks ADC1 ADC3 ADC5 ADC2 ADC4 ADC6 CX_SDOUT SAI_SDOUT...
Page 32: Adcin1/Adcin2 Serial Data Format
Figure 15. ADCIN1/ADCIN2 Serial Audio Format For proper operation, the CS42526 must be configured to select which SCLK/LRCK is being used to clock the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 51, must be set accordingly.
Page 33: One Line Mode(Olm) Configurations
CS42526 4.6.4 One Line Mode(OLM) Configurations 4.6.4a OLM Config #1 One Line Mode Configuration #1 can support up to 6 channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data. This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.
Page 34: Olm Config #2
CS42526 4.6.4b OLM Config #2 This configuration will support up to 6 channels of DAC data, 6 channels of ADC data and no channels of S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 96 kHz on all chan- nels for both the DAC and ADC.
Page 35: Olm Config #3
CS42526 4.6.4c OLM Config #3 This One Line Mode configuration #3 will support up to 6 channels of DAC data, 6 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 20-bit samples at a sampling frequency of 48kHz on all channels for both the DAC and ADC.
Page 36: Olm Config #4
CS42526 4.6.4d OLM Config #4 This configuration will support up to 6 channels of DAC data, 6 channels of ADC data and no channels of S/PDIF received data. OLM Config #4 will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz.
Page 37: Olm Config #5
CS42526 4.6.4e OLM Config #5 This One-Line Mode configuration can support up to 6 channels of DAC data, 2 channels of ADC data and 2 channels of S/PDIF received data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.
Page 38: Control Port Description And Timing
4.7.1 SPI Mode In SPI mode, CS is the CS42526 chip select signal, CCLK is the control port bit clock (input into the CS42526 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Page 39: I 2 C Mode
All other transitions of SDA occur while the clock is low. The first byte sent to the CS42526 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write).
Page 40: Interrupts
When RST is low, the CS42526 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes oper- ational and the desired settings should be loaded into the control registers.
Page 41 The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42526 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and PLL.
Page 42: Register Quick Reference
CS42526 5. REGISTER QUICK REFERENCE Addr Function Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 page 46 default Power Con- PDN_RCVR1 PDN_RCVR0 PDN_ADC Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 trol page 47 default Functional CODEC_FM1 CODEC_FM0 SAI_FM1 SAI_FM0 ADC_SP ADC_SP DAC_DEM RCVR_DEM...
Page 43 CS42526 Addr Function Channel Reserved Reserved B3_MUTE A3_MUTE B2_MUTE A2_MUTE B1_MUTE A1_MUTE Mute page 58 default Vol. Control A1_VOL7 A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0 page 58 default Vol. Control B1_VOL7 B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0 page 58 default Vol.
Page 44 CS42526 Addr Function ADC Right Reserved Reserved RGAIN5 RGAIN4 RGAIN3 RGAIN2 RGAIN1 RGAIN0 Ch. Gain page 61 default RCVR Mode SP_SYNC Reserved DE-EMPH1 DE-EMPH0 INT1 INT0 HOLD1 HOLD0 Ctrl page 61 default RCVR Mode Reserved TMUX2 TMUX1 TMUX0 Reserved RMUX2...
Page 45 CS42526 Addr Function RXP5/GPO Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 69 default RXP4/GPO Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 69 default RXP3/GPO Mode1 Mode0 Polarity Function4 Function3 Function2 Function1 Function0 page 69 default RXP2/GPO...
Page 46: Register Description
Rev_ID2 Rev_ID1 Rev_ID0 6.2.1 CHIP I.D. (CHIP_IDX) Default = 1111 Function: I.D. code for the CS42526. Permanently set to 1111. 6.2.2 CHIP REVISION (REV_IDX) Default = 0100 Function: CS42526 revision level. Revision D is coded as 0100. Revision C is coded as 0011.
Page 47: Power Control (Address 02H)
CS42526 Power Control (address 02h) PDN_RCVR1 PDN_RCVR0 PDN_ADC Reserved PDN_DAC3 PDN_DAC2 PDN_DAC1 6.3.1 POWER DOWN RECEIVER (PDN_RCVRX) Default = 10 00 - Receiver and PLL in normal operational mode. 01 - Receiver and PLL held in a reset state. Equivalent to setting 11.
Page 48: Functional Mode (Address 03H)
CS42526 Functional Mode (address 03h) CODEC_FM1 CODEC_FM0 SAI_FM1 SAI_FM0 ADC_SP SEL1 ADC_SP SEL0 DAC_DEM RCVR_DEM 6.4.1 CODEC FUNCTIONAL MODE (CODEC_FMX) Default = 00 00 - Single-Speed Mode (4 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates)
Page 49: Interface Formats (Address 04H)
CS42526 in the Receiver Mode Control (address 1Eh) register to set the appropriate sample rate. DAC_DEM FRC_PLL_LK DE-EMPH[1:0] De-Emphasis reg03h[1] reg06h[0] reg1Eh[5:4] Mode No De-Emphasis Auto-Detect Fs Reserved 32 kHz 44.1 kHz 48 kHz Table 5. DAC De-Emphasis 6.4.5 RECEIVER DE-EMPHASIS CONTROL (RCVR_DEM)
Page 50: Table 7. Digital Interface Formats
CS42526 DIF1 DIF0 Description Format Figure Left Justified, up to 24-bit data S, up to 24-bit data Right Justified, 16-bit or 24-bit data reserved Table 7. Digital Interface Formats 6.5.2 ADC ONE_LINE MODE (ADC_OLX) Default = 00 Function: These bits select which mode the ADC will use. By default one-line mode is disabled but can be se- lected using these bits.
Page 51: Misc Control (Address 05H)
CS42526 6.5.5 CODEC RIGHT JUSTIFIED BITS (CODEC_RJ16) Default = 0 Function: This bit determines how many bits to use during right justified mode for the DAC and ADC within the CODEC Serial Port. By default the DAC and ADC will be in RJ24 bits but can be set to RJ16 bits.
Page 52: Clock Control (Address 06H)
CS42526 6.6.5 HIGH PASS FILTER FREEZE (HPF_FREEZE) Default = 0 Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Dig- ital Filter Characteristics”...
Page 53: Table 11. Omck Frequency Settings
PLL LOCK TO LRCK (PLL_LRCK) Default = 0 0 - Disabled 1 - Enabled Function: When enabled, the internal PLL of the CS42526 will lock to the SAI_LRCK of the SAI serial port. 6.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX) Default = 00 Function: These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)”...
Page 54: Omck/Pll_Clk Ratio (Address 07H) (Read Only)
The CS42526 will auto-detect a digital silence condition when 1548 consecutive zeros have been de- tected. 6.9.2 AES FORMAT DETECTION (AES FORMATX) Default = xxx Function: The CS42526 will auto-detect the AES format of the incoming S/PDIF stream and display the infor- mation according to the following table. Description Format2 Format1 Format0...
Page 55: Burst Preamble Pc And Pd Bytes (Addresses 09H - 0Ch)(Read Only)
Default = xxx Function: The CS42526 will auto-detect the ratio between the OMCK and the recovered clock from the PLL, which is displayed in register 07h. Based on this ratio, the absolute frequency of the PLL clock can be determined, and this information is displayed according to the following table. If the absolute fre- quency of the PLL clock does not match one of the given frequencies, this register will display the closest available value.
Page 56: Volume Transition Control (Address 0Dh)
CS42526 6.11 Volume Transition Control (address 0Dh) Reserved SNGVOL SZC1 SZC0 AMUTE MUTE SAI_SP RAMP_UP RAMP_DN 6.11.1 SINGLE VOLUME CONTROL (SNGVOL) Default = 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the A1 Channel Volume Control register and the other Volume Control registers are ignored.
Page 57 1 - Enabled Function: The Digital-to-Analog converters of the CS42526 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the MUTEC pin will go active during the mute period.
Page 58: Channel Mute (Address 0Eh)
1 - Enabled Function: The Digital-to-Analog converter outputs of the CS42526 will mute when enabled. The quiescent volt- age on the outputs will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]).
Page 59: Mixing Control Pair 1 (Channels A1 & B1)(Address 18H) Mixing Control Pair 2 (Channels A2 & B2)(Address 19H) Mixing Control Pair 3 (Channels A3 & B3)(Address 1Ah)
CS42526 6.15 Mixing Control Pair 1 (Channels A1 & B1)(address 18h) Mixing Control Pair 2 (Channels A2 & B2)(address 19h) Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) Px_A=B Reserved Reserved Px_ATAPI4 Px_ATAPI3 Px_ATAPI2 Px_ATAPI1 Px_ATAPI0 6.15.1 CHANNEL A VOLUME = CHANNEL B VOLUME (PX_A=B)
Page 60: Table 16. Atapi Decode
6.15.2 ATAPI CHANNEL MIXING AND MUTING (PX_ATAPIX) Default = 01001 Function: The CS42526 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to Table 16 and Figure 8 for additional information. ATAPI4...
Page 61: Adc Left Channel Gain (Address 1Ch)
CS42526 6.16 ADC Left Channel Gain (address 1Ch) Reserved Reserved LGAIN5 LGAIN4 LGAIN3 LGAIN2 LGAIN1 LGAIN0 6.16.1 ADC LEFT CHANNEL GAIN (LGAINX) Default = 00h Function: The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and Zero Cross bits (SZC[1:0]) from +15 to -15 dB.
Page 62: Receiver Mode Control 2 (Address 1Fh)
CS42526 6.18.2 DE-EMPHASIS SELECT BITS (DE-EMPHX) Default = 00 00 - Reserved 01 - De-Emphasis for 32 kHz sample rate. 10 - De-Emphasis for 44.1 kHz sample rate. 11 - De-Emphasis for 48 kHz sample rate. Function: Used to specify which de-emphasis filter to apply when the “Force PLL Lock (FRC_PLL_LK)” on page 53 is enabled.
Page 63: Interrupt Status (Address 20H) (Read Only)
CS42526 TMUX2 TMUX1 TMUX0 Description Output from pin RXP6 Output from pin RXP7 Table 18. TXP Output Selection 6.19.2 RECEIVER MULTIPLEXER (RMUXX) Default = 000 Function: Selects which of the eight receiver inputs will be mapped to the internal receiver.
Page 64: Interrupt Mask (Address 21H)
Indicates when the user status buffer has changed. 6.20.5 ADC OVERFLOW (OVERFLOW) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS42526 ADC signal path. 6.20.6 RECEIVER ERROR (RERR) Default = 0 Function: Indicates that a receiver error has occurred. The register “Receiver Errors (address 26h) (Read Only)”...
Page 65: Channel Status Data Buffer Control (Address 24H)
CS42526 01 - Falling edge active 10 - Level active 11 - Reserved 6.23 Channel Status Data Buffer Control (address 24h) Reserved LOCKM Reserved Reserved Reserved BSEL 6.23.1 SPDIF RECEIVER LOCKING MODE (LOCKM) Default = 1 0 - Revision C compatibility mode.
Page 66: Receiver Channel Status (Address 25H) (Read Only)
CS42526 6.24 Receiver Channel Status (address 25h) (Read Only) AUX3 AUX2 AUX1 AUX0 AUDIO COPY ORIG The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control register.
Page 67: Receiver Errors (Address 26H) (Read Only)
CS42526 Function: A ‘0’ indicates that the received data is 1st generation or higher. A ‘1’ indicates that the received data is original. COPY and ORIG will both be set to ‘1’ if the incoming data is flagged as professional, or if the receiver is not in use.
Page 68: Receiver Errors Mask (Address 27H)
CS42526 Indicates the received confidence status. This bit is updated on sub-frame boundaries. 6.25.6 BI-PHASE ERROR (BIP) Default = x 0 - No error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. Function: Indicates a bi-phase coding error. This bit is updated on sub-frame boundaries.
Page 69: Rxp/General Purpose Pin Control (Addresses 29H To 2Fh)
CS42526 0 - Channel mute is not mapped to the MUTEC pin 1 - Channel mute is mapped to the MUTEC pin Function: Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are mapped, then the MUTEC pin is driven to the "active"...
Page 70 CS42526 ignored. It is recommended that in this mode this bit be set to 0. 6.28.3 FUNCTIONAL CONTROL (FUNCTIONX) Default = 00000 Function: RXP Input - If the pin is configured for an RXP input, the functional bits are ignored. It is recommended that in this mode all the functional bits be set to 0.
Page 71: Q-Channel Subcode Bytes 0 To 9 (Addresses 30H To 39H) (Read Only)
CS42526 6.29 Q-Channel Subcode Bytes 0 to 9 (addresses 30h to 39h) (Read Only) Address3 Address2 Address1 Address0 Control3 Control2 Control1 Control0 Track7 Track6 Track5 Track4 Track3 Track2 Track1 Track0 Index7 Index6 Index5 Index4 Index3 Index2 Index1 Index0 Minute7 Minute6...
Page 72: Parameter Definitions
CS42526 7. PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal.
Page 73: References
Digital Audio Transmission, by Clifton Sanchez.; an excellent tutorial on SCMS. It is available from the AES as preprint 3518. 6) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Con- verter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Con- vention of the Audio Engineering Society, September 1997.
Page 74: Package Dimensions
CS42526 9. PACKAGE DIMENSIONS 64L LQFP PACKAGE DRAWING ∝ INCHES MILLIMETERS 0.55 0.063 1.40 1.60 0.002 0.004 0.006 0.05 0.10 0.15 0.007 0.008 0.011 0.17 0.20 0.27 0.461 0.472 BSC 0.484 11.70 12.0 BSC 12.30 0.390 0.393 BSC 0.398 9.90 10.0 BSC...
Page 75: Appendix A: External Filters
10.2 DAC Output Filter The CS42526 is a linear phase design and does not include phase or amplitude compensation for an ex- ternal filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
Page 76: Appendix B: S/Pdif Receiver
The CS42526 also contains sufficient RAM to store a full block of C data for both A and B channels (192 x 2 = 384 bits), and also 384 bits of User (U data) information. The user may read from these buffer RAMs through the control port.
Page 77: Channel Status Data E Buffer Access
E buffer. In this mode, a read will cause the CS42526 to output two bytes from its control port. The first byte out will represent the A channel status data, and the second byte will represent the B channel status data.
Page 78: Serial Copy Management System (Scms)
Channel Status section. The user has access to the E buffer through the control port Data Buffer which is mapped into the register space of the CS42526. The Data Buffer must first be configured to point to the address space of the U data. This is accomplished by setting the BSEL bit to ‘1’ in the reg- ister “Channel Status Data Buffer Control (address 24h)”...
Page 79: Appendix C: Pll Filter
CS42526 12. APPENDIX C: PLL FILTER The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update infor- mation to the PLL. This results in the PLL being immune to data dependent jitter effects because the S/PDIF preambles do not vary with the data.
Page 80: External Filter Components
CS42526 12.1 External Filter Components 12.1.1 General The PLL behavior is affected by the external filter component values in the Typical Connection Diagrams. Figure 5 show the recommended configuration of the two capacitors and one resistor that comprise the PLL filter. The external PLL component values listed in Table 21 have a high corner frequency jitter atten- uation curve, take a short time to lock, and offer good output jitter performance.
Page 81: Capacitor Selection
CS42526 12.1.3 Capacitor Selection The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit.
Page 82: Appendix D: External Aes3/Spdif/Iec60958 Receiver Components
13. APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS 13.1 AES3 Receiver External Components The CS42526 AES3 receiver is designed to accept only consumer-standard interfaces. The standards call for an unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector is an RCA phono socket.
Page 83: Appendix E: Adc Filter Plots
CS42526 14. APPENDIX E: ADC FILTER PLOTS -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 33. Single Speed Mode Stopband Rejection Figure 34.
Page 84: Figure 39. Double Speed Mode Transition Band (Detail)
CS42526 ‘ 0.10 0.08 0.05 0.03 0.00 -0.03 -0.05 -0.08 -0.10 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) Frequency (normalized to Fs) Figure 39. Double Speed Mode Transition Band (Detail) Figure 40.
Page 85: Appendix F: Dac Filter Plots
CS42526 15. APPENDIX F: DAC FILTER PLOTS 0.42 0.44 0.46 0.48 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 45. Single Speed (fast) Stopband Rejection Figure 46. Single Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01...
Page 86: Figure 51. Single Speed (Slow) Transition Band (Detail)
CS42526 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.05 0.15 0.25 0.35 0.45 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 51. Single Speed (slow) Transition Band (detail) Figure 52. Single Speed (slow) Passband Ripple 0.42...
Page 87: Figure 57. Double Speed (Slow) Stopband Rejection
CS42526 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 57. Double Speed (slow) Stopband Rejection Figure 58. Double Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0.005 0.01 0.015 0.02 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 0.05 0.15...
Page 88: Figure 63. Quad Speed (Fast) Transition Band (Detail)
CS42526 0.15 0.05 0.05 0.15 0.05 0.15 0.25 0.45 0.46 0.47 0.48 0.49 0.51 0.52 0.53 0.54 0.55 Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 63. Quad Speed (fast) Transition Band (detail) Figure 64. Quad Speed (fast) Passband Ripple Frequency(normalized to Fs) Frequency(normalized to Fs) Figure 65.
Page 89: Table 22. Revision History
CS42526 Table 22. Revision History Release Date Changes December 2002 Advance Release August 2003 Preliminary Release August 2003 – Added Revision History table. – Updated registers 6.7.4 and 6.7.5 on page 53. March 2004 Corrected error in document title. July 2004...
Page 90 ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

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