Avaya S8700 Maintenance Manual page 190

Additional Maintenance Procedures
The second part of the test sends the standard DS1 3-in-24 stress testing pattern
from the DS1 board, through the loopback jack, and back to a bit error detector
and counter on the DS1 board. The bit error rate counter may be examined on
the management terminal, and provides the results of the second part of the test.
The test remains in this state until it is terminated so that the CPE wiring may be
bit error rate tested for as long as desired.
1. Busy out the DS1 circuit pack by entering busyout board UUCSS.
2. At the management terminal, enter change ds1 location and verify the
near-end csu type is set to integrated.
3. On page 2 of the DS1 administration form, confirm that the TX LBO field
is 0 (dB). If not, record the current value and change it to 0 dB for testing.
Press
4. Enter test ds1-loop location cpe-loopback-jack. This turns on simplex
power to the loopback jack and waits about 20 seconds for any active DS1
facility alarms to clear. A "PASS" or "FAIL" displays on the terminal. This is
the first of the two results. A "FAIL" indicates a fault is present in the wiring
between the ICSU and the loopback jack. The loopback jack may also be
faulty. A "PASS" only indicates that the loopback jack looped successfully,
and not that the test data contains no errors. If a "PASS" is obtained,
continue with the following steps.
5. Enter clear meas ds1 loop location to clear the bit error count.
6. Enter clear meas ds1 log location to clear the performance measurement
counts.
7. Enter clear meas ds1 esf location to clear the ESF error count.
8. Enter list meas ds1 sum location to display the bit error count. Refer to
Table 5-1 on page 5-5
5-4 Issue 1 May 2002
to implement the changes or press
Enter
NOTE:
The loss of signal (LOS) alarm (demand test #138) is not processed
during this test while the 3-in-24 pattern is active.
for troubleshooting information.
to change nothing.
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