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118 Appendix C: BIOS reference for Matrox Supersight SHB-5520
Item
Limit CPUID Maximum
Disabled*
Enabled
Execute Disable Bit
Disabled
Enabled*
Hardware Prefetcher
Disabled
Enabled*
Adjacent Cache Line Prefetch
Disabled
Enabled*
L1 Data Prefetcher
Disabled
Enabled*
Data Reuse Optimization
Disabled
Enabled*
Meaning
This item allows you to enable the maximum CPUID value limit. Older operating systems (such as Microsoft
Windows 95/98/ME) do not support the values returned by CPUID instructions of newer processors. This
item can be used to limit the value returned by the CPUID instruction to 03h, so that older operating systems
work with newer CPUs.
Note that the default setting of this value is optimized for the Matrox Supersight SHB-5520 board.
❖
This item allows you to enable the execute-disable bit capability of the CPU. The execute-disable bit
capability of the CPU provides enhanced virus protection. This capability allows memory to be marked as
executable or non-executable, allowing the CPU to raise an error to the operating system if malicious code
attempts to run in non-executable memory, thereby preventing the malicious code from infecting the unit.
When set to Enabled, the execute-disable bit capability of the CPU is enabled.
When set to Disabled, the execute-disable bit capability of the CPU is disabled, and the execute-disable bit
flag will always return a 0 (indicating that there is no malicious code attempting to run in non-executable
memory).
Note that the default setting of this value is optimized for the Matrox Supersight SHB-5520 board.
❖
This item allows you to enable the hardware prefetcher option of the processor. Prefetching allows the
processor to fetch instructions and/or data from memory into the cache well before the processor needs it,
therefore improving the load-to-use latency and increasing processor performance. The hardware prefetcher
operates transparently, without programmer intervention, to fetch streams of data and instruction from
memory into the second-level (L2) cache.
Note that the default setting of this value is optimized for the Matrox Supersight SHB-5520 board.
❖
This item allows you to enable the adjacent cache line prefetch option of the processor.
When set to Enabled, the CPU will fetch two adjacent cache lines (each cache line is 64 bytes) when
updating the cache, rather than fetching a single cache line. Like the Hardware Prefetcher item above, the
adjacent cache line prefetch works transparently, without programmer intervention.
When set to Disabled, this item can reduce bus traffic.
Note that the default setting of this value is optimized for the Matrox Supersight SHB-5520 board.
❖
This item allows you to enable the data prefetcher for the L1 data cache.
When set to Enabled, the L1 data prefetcher is used to speed up data fetch and store operations.
Note that the default setting of this value is optimized for the Matrox Supersight SHB-5520 board.
❖
This item allows you to reduce the frequency of L3 cache updates from the L1 cache. This might improve
performance by reducing the internal bandwidth consumed by constantly updating L1 cache lines in the L3
cache.
Note that you should only change this item after performing application benchmarking to verify which setting
❖
best improves your application's performance.
When set to Disabled, this item might results in more fetches to main memory.
When set to Enabled, this item might speed up some repetitive tasks that rely upon buffering, moving, or
modifying repeated data.
Note that the default setting of this value is optimized for the Matrox Supersight SHB-5520 board.
❖
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