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21.5.1.12 MDR Register (Offset = 808h) [reset = 0h]
MDR is shown in
Figure 21-25
Master Data
This register contains the data to be transmitted when in the Master Transmit state and the data received
when in the Master Receive state.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Field
31-8
RESERVED
7-0
DATA
SWCU117C – February 2015 – Revised September 2015
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and described in
Table
Figure 21-25. MDR Register
RESERVED
R-0h
Table 21-14. MDR Register Field Descriptions
Type
Reset
Description
R
0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W
0h
When Read: Last RX Data is returned
When Written: Data is transferred during TX transaction
Copyright © 2015, Texas Instruments Incorporated
21-14.
9
8
7
Inter-Integrated Circuit (I
2
I
C Registers
6
5
4
3
2
1
0
DATA
R/W-0h
1421
2
C) Interface
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