Irq Sense Control Register (Iscr) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

5.2.5 IRQ Sense Control Register (ISCR)

ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ , IRQ
5
Bit 7
—
Initial value 0
Read/Write R/W
Reserved bits
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3, and 2—Reserved: These bits are readable/writable and do not affect selection of
level sensing or falling-edge sensing.
Bits 5, 4, 1, and 0—IRQ
IRQ0SC): These bits selects whether interrupts IRQ
sensing of pins IRQ
Bits 5, 4, 1, and 0
IRQ5SC, IRQ4SC,
IRQ1SC, IRQ0SC
0
1
, IRQ , and IRQ
4 1
6 5
— IRQ5SC
0 0
R/W R/W
IRQ and IRQ sense control
5
These bits select level sensing or falling-edge
sensing for IRQ
, IRQ , IRQ
5 4 1
, IRQ , IRQ , IRQ
5 4 1 0
Description
Interrupts are requested when IRQ
inputs are low
Interrupts are requested by falling-edge input at IRQ
IRQ , IRQ , IRQ
4 1
0
4 3
IRQ4SC —
0 0
R/W R/W
Reserved bits
4
and IRQ interrupts
5 4
IRQ and IRQ sense control
1
These bits select level sensing or falling-edge
sensing for IRQ
, and IRQ Sense Control (IRQ5SC, IRQ4SC, IRQ1SC,
, 0
, IRQ
5 4
or by falling-edge sensing.
5
0
2 1
— IRQ1SC
0 0
R/W R/W
0
and IRQ
1 0
, IRQ , IRQ are requested by level
1 0
, IRQ , IRQ , IRQ
4 1 0
,
5
0
IRQ0SC
0
R/W
interrupts
(Initial value)
93