Table 6-1 Sai Interrupt Vector Locations; Table 6-2 Sai Internal Interrupt Priorities; Baud Rate Control Register (Brc) - Motorola DSP56009 User Manual

Interrupt
Left Channel Transmit
Right Channel Transmit
Transmit Exception
Left Channel Receive
Right Channel Receive
Receive Exception
Priority
Highest
Lowest
6.3.1

Baud Rate Control Register (BRC)

The serial clock frequency is determined by the control bits in the Baud Rate Control
register (BRC) as described in the following paragraphs. The BRC is illustrated in
Figure 6-4 on page 6-8. The maximum allowed internally generated bit clock
frequency is f /4 and the maximum allowed external bit clock frequency is f
osc
BRC bits should be modified only when the baud-rate generator is disabled (i.e.,
when both receiver and transmitter sections are defined as slaves or when both are in
the individual reset state); otherwise improper operation may result. When read by
the DSP, the BRC appears on the two low-order bytes of the 24-bit word, and the
high-order byte is read as 0s. The BRC is cleared during hardware reset and software
reset.
MOTOROLA

Table 6-1 SAI Interrupt Vector Locations

TXIL = 0
P: $0010
P: $0012
P: $0014
—
—
—

Table 6-2 SAI Internal Interrupt Priorities

SAI Receive
SAI Transmit
SAI Left Channel Receive
SAI Left Channel Transmit
SAI Right Channel Receive
SAI Right Channel Transmit
DSP56009 User's Manual
Serial Audio Interface Programming Model
TXIL = 1 RXIL = 0
P: $0040
P: $0042
P: $0044
— P: $0016
— P: $0018
— P: $001A
Interrupt
Serial Audio Interface
RXIL = 1
— —
— —
— —
P: $0046
P: $0048
P: $004A
/3.
osc
6-9