Figure 4-24 Slow Read Or Write Dram Access Timing-6 - Motorola DSP56009 User Manual

Figure 4-24 shows the timing using Relative Addressing mode for a 24-bit
word/4-bit bus memory access. The numbers in the table are memory access clock
cycles and correspond to clock cycles of the timing figure directly below.
Set up row address
R/W Bits 23–20
R/W Bits 19–16
R/W Bits 15–12
R/W Bits 11–8
R/W Bits 7–4
R/W Bits 3–0
Finish last R/W cycle
New memory cycle
CLK
Address
MRAS
MCAS
Read
MRD
MWR
Data In
Write
MWR
MRD
Data Out
Figure 4-24 Slow Read or Write DRAM Access Timing—6
MOTOROLA
24-bit word/4-bit bus—Relative Addressing
1 2 3 4
5
9 10 11 12
13 14 15 16
17 18 19 20
21 22 23 24
Row
Address
DSP56009 User's Manual
External Memory Interface
6 7 8
25 26 27 28
Column Last Column
Address Address
Valid Valid
Data Data
Valid Valid
Data Data
EMI Timing
29 30 31 32
1 2
Row
Address
AA0414
4-63