Figure 4-6 Timing Diagram Of A Dram Refresh Cycle (Fast); Figure 4-7 Timing Diagram Of A Dram Refresh Cycle (Slow) - Motorola DSP56009 User Manual

Figure 4-6 shows the timing for a DRAM refresh cycle when fast timing is selected.
Figure 4-7 shows the timing for a DRAM refresh cycle when slow timing is selected.
Note: Timer resolution is for a prescaling of 8. The refresh timer initiates a refresh
request every (ECD set + 1) × prescale.
1 2
CLK
MRAS
MCAS
During a Refresh Cycle: MCSx, MRD and MWR are deasserted (high),

Figure 4-6 Timing Diagram of a DRAM Refresh Cycle (Fast)

1 2
CLK
MRAS
MCAS
During a Refresh Cycle: MCSx, MRD and MWR are deasserted (high),

Figure 4-7 Timing Diagram Of a DRAM Refresh Cycle (Slow)

MOTOROLA
3 4 5
data lines remain high impedance, and
address lines remain unchanged.
3 4 5 6
data lines remain high impedance, and
address lines remain unchanged.
DSP56009 User's Manual
External Memory Interface
6 7 8
7 8 9 10
DRAM Refresh
9 1 2
11 12 13 1
AA0298k
2
AA0299
4-37