Motorola DSP56009 User Manual page 25

– Up to 40.5 Million Instructions Per Second (MIPS)—24.69 ns instruction
cycle at 81 MHz
– Up to 324 Million Operations Per Second (MOPS) at 81 MHz
– On-chip peripheral registers memory-mapped in data memory space
– Three external interrupt request pins
– Data Arithmetic Logic Unit (ALU), Program Control (PC), and Address
Generation Unit (AGU) all integral to the core processor
– Bootstrap loading from SHI or EMI (in absolute SRAM mode)
– Completely pin-compatible with DSP56004 and DSP56007 for easy
upgrades
– Fully static, HCMOS design for operating frequencies from 81 MHz down
to DC
– 80-pin plastic Quad Flat Pack surface-mount package; 14 × 14 × 2.45 mm;
0.65 mm lead pitch
– Highly parallel instruction set with unique DSP addressing modes
– Two 56-bit accumulators, including extension byte
– Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock
cycles)
– Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction
cycles
– 56-bit addition/subtraction in 1 instruction cycle
– Fractional and integer arithmetic with support for multiprecision
arithmetic
– Hardware support for block-floating point Fast Fourier Transforms (FFTs)
– Zero-overhead fast interrupts (2 instruction cycles)
– Nested hardware DO loops
• Memory Modules:
– On-chip 4352 × 24-bit Y data RAM and 1792 × 24-bit Y data ROM
– On-chip 4608 × 24-bit X data RAM and 3072 × 24-bit X data ROM
– On-chip 10240 × 24-bit Program ROM
– On-chip 512 × 24-bit Program RAM and 64 × 24-bit bootstrap ROM
MOTOROLA DSP56009 User's Manual
Overview
DSP56009 Features
1-7