Figure 4-23 Slow Read Or Write Dram Access Timing-5 - Motorola DSP56009 User Manual

External Memory Interface
EMI Timing
Figure 4-23 shows the timing using Relative Addressing mode for a 20-bit
word/4-bit bus memory access. The numbers in the table are memory access clock
cycles and correspond to clock cycles of the timing figure directly below. Data
accesses are left justified such that the 20-bit word is read from and written into the
upper-most portion of the 24-bit word (bits 23–4).
Set up row address
R/W Bits 23–20
R/W Bits 19–16
R/W Bits 15–12
R/W Bits 11–8
R/W Bits 7–4
Finish last R/W cycle
New memory cycle
CLK
Address
MRAS
MCAS
Read
MRD
MWR
Data In
Write
MWR
MRD
Data Out
Figure 4-23 Slow Read or Write DRAM Access Timing—5
4-62
20-bit word/4-bit bus—Relative Addressing
1 2 3 4
5
9 10 11 12
13 14 15 16
17 18 19 20
Row
Address
DSP56009 User's Manual
6 7 8
21 22 23 24
Column Last Column
Address Address
Valid Valid
Data Data
Valid Valid
Data Data
25 26 27 28
1 2
Row
Address
AA0413
MOTOROLA