Table 4-18 Continuous Refresh: Timings And Settings For Eps[1:0] And Ecd[7:0]; Table 4-19 Burst Refresh: Timings And Settings For Eps[1:0] And - Motorola DSP56009 User Manual

External Memory Interface
DRAM Refresh

Table 4-18 Continuous Refresh: Timings And Settings For EPS[1:0] And ECD[7:0]

DSP Clock
Frequency
40 MHz
50 MHz
66 MHz
81 MHz
Note:
Table 4-19 shows the timings and bit settings for burst refresh cycles, cross-
referenced to appropriate clock frequencies.
Note: The DRAMs are usually required to refresh all rows within a certain time. This
time does not change for DRAMs of different sizes.
Table 4-19 Burst Refresh: Timings And Settings For EPS[1:0] And ECD[7:0]
Fast Timing Mode/
DSP Clock
Slow Timing Mode
Frequency
(1 Refresh Cycle)
40 MHz
50 MHz
66 MHz
81 MHz
4-36
Max Time
Between
Refresh
Cycles
15.6 µs
124.8 µs
15.6 µs
124.8 µs
15.6 µs
124.8 µs
15.6 µs
124.8 µs
Timer resolution is for a prescaling of 8. The refresh timer
initiates a refresh request every (ECD set + 1) × prescale.
Max Time
To Refresh
512 Rows
0.225 µs
8 ms
0.325 µs
64 ms
0.180 µs
8 ms
0.260 µs
64 ms
0.136 µs
8 ms
0.197 µs
64 ms
n.a. 8 ms
0.161 µs
64 ms
DSP56009 User's Manual
EPS ECD
Setting Setting
15.6 µs
01 77
124.8 µs
00 77
15.52 µs
01 96
124.2 µs
00 96
15.52 µs
01 127
124.2 µs
00 127
15.6 µs
01 157
124.8 µs
00 157
EPS ECD
Setting Setting
10
10
10
10
10
10
n.a.
10
Actual
Time
Between
Refresh
Cycles
% Of Execution
Code Time EREF
is Set
(Fast/Slow)
8 1.44% / 2.08%
12 0.18% / 0.26%
8 1.15% / 1.66%
12 0.14% / 0.21%
8 0.87% / 1.26%
12 0.11% / 0.16%
n.a. n.a. / 1.03%
12 n.a. / 0.13%
MOTOROLA