Motorola DSP56009 User Manual page 265

HFIFO (HCSR FIFO Enable Control) 5-14
HFM0-HFM1 (HCKR Filter Mode) 5-12
HI2C (HCSR Serial Host Interface I2C/SPI
Selection) 5-13
HIDLE (HCSR Idle) 5-15
HM0-HM1 (HCSR Serial Host Interface
Mode) 5-14
HMST (HCSR Master Mode) 5-14
Host
Receive Data FIFO (HRX) 5-9
Receive Data FIFO—DSP Side 5-9
Transmit Data Register (HTX) 5-8
Transmit Data Register—DSP Side 5-8
HREQ Function In SHI Slave Modes 5-15
HRFF (HCSR Host Receive FIFO Full) 5-18
HRIE0-HRIE1 (HCSR Receive Interrupt
Enable) 5-16
HRNE (HCSR Host Receive FIFO Not
Empty) 5-18
HROE (HCSR Host Receive Overrun Error) 5-18
HRQE0-HRQE1 (HCSR Host Request
Enable) 5-15
HTDE (HCSR Host Transmit Data Empty) 5-17
HTIE (HCSR Transmit Interrupt Enable) 5-16
HTUE (HCSR Host Transmit Underrun
Error) 5-17
I
, ,
I2C 1-18 5-3 5-20
Bit Transfer 5-20
Bus Protocol For Host Read Cycle 5-23
Bus Protocol For Host Write Cycle 5-23
Data Transfer Formats 5-22
Master Mode 5-28
Protocol for Host Read Cycle 5-23
Protocol for Host Write Cycle 5-23
Receive Data In Master Mode 5-29
Receive Data In Slave Mode 5-26
Slave Mode 5-26
Start and Stop Events 5-21
Transmit Data In Master Mode 5-30
Transmit Data In Slave Mode 5-27
I2C Bus Acknowledgment 5-22
I2C Mode 5-3
,
I2S Format 1-19 6-3
Input/Output 1-16
Instruction Set Summary B-7
Inter Integrated Circuit Bus 1-18
Internal Exception Priorities
SHI 5-7
MOTOROLA
Internal Interrupt Priorities
Interrupt
Interrupt and Mode Control Signals 2-10
Interrupt Priority Level (IPL) 3-14
Interrupt Priority Register (IPR) 3-14
Interrupt Vectors
Interrupts — See Section 3
L
Low Power Divider 1-12
M
Manual Conventions 1-5
Maximum DSP Clock Frequencies
MEC Format 1-19
Memories 1-13
Memory — See Section 3
Memory Maps 1-16
MF0-MF11 (PLL Multiplication Factor bits) 3-18
Multiplication Factor (MF0-MF11) 3-18
O
OMR (Operating Mode Register) B-16
On 2-22
OnCE Debug Mode Consideration 4-32
OnCE port signal descriptions 2-22
OnCE port Signals 2-22
On-Chip Emulation (OnCE) Port 1-13
On-Chip Emulation Port Signals 2-22
On-chip Peripherals Memory Map 1-16
Operating Mode Bits 3-11
Operating Mode Bits (MC, MB, MA) 3-11
Operating Mode Register (OMR) 3-11
Operating Modes 3-12
Operating Modes — See Section 3
P
,
5-3
PCTL (PLL Control Register) B-17
PEN (PLL Enable) 2-7
Peripheral Memory Map 1-16
DSP56009 User's Manual
SAI 6-9
,
Sources 1-13 B-5
Starting Addresses 1-13
EMI 4-5
SHI 5-7
when using DRAM 4-50
when using EROM 4-51
when using SRAM 4-51
,
6-3
,
B-4
,
3-13
I
,
B-5
,
4-34
,
B-4
,
B-16
,
B-4
Index-3