Motorola DSP56009 User Manual page 282

F
Memory Wrap Interrupt Enable 4-17
Read/Write Interrupt Select 4-17
EOR 4-8
ERCR
Refresh Enable 4-23
Exception Prioriies 4-5
External Memory Interface 1-10
Features 4-4
Interrupt Select 4-17
Interrupt Vectors 4-5
Locations Per Word 4-10
Memory Accesses Per Word 4-10
Off Line Refresh 4-34
,
Offset Register 4-7
On Line Refresh 4-33
Operating Considerations 4-38
Operation During STOP 4-45
Operation During WAIT 4-45
Pipeline 4-39
Programming Model 4-5
Read Data Transfer 4-40
Refresh Control Register 4-21
Refresh Timer 4-33
Software Controlled Refresh 4-34
SRAM Absolute Addressing 4-24
SRAM Relative Addressing 4-25
SRAM Timing 4-20
SRAM Word Storage Locations 4-13
Timing 4-50
Triggering and Pipelining 4-38
Word Length 4-11
Write Data Transfer 4-43
Write Ofset Register (EWOR) 4-7
EMI Operating States 2-9
EMWIE (ECSR EMI Memory Wrap Interrupt
Enable 4-17
EOSR (EMI One-Shot Refresh) 4-22
EOSR (ERCR One-Shot Refresh) 4-22
EPS0-EPS1 (EMI Refresh Clock Prescaler) 4-22
ERCR (EMI Refresh Control Register) 4-21
ERED (EMI Refresh Enable When
Debugging) 4-22
ERED (ERCR Refresh Enable When
Debugging) 4-22
EREF (EMI Refresh Enable) 4-23
ERTS (EMI Read Trigger Select) 4-19
ESTM0-ESTM3 (EMI SRAM Memory
Timing) 4-20
EWL0-EWL2 (EMI Word Length) 4-11
Index-2
4-8
DSP56009 User's Manual
EWOR (EMI Write Offset Register) 4-7
Examples C-1
External
Memory Interface — See Section 4
External Memory Interface (EMI) 1-10
External Memory Interface (EMI) Signals 2-7
F
Fast Read or Write DRAM Access Timing 4-52
, , ,
4-53 4-54 4-55 4-56
FIR Filter (3 Tap) C-10
FIR Filter Program C-10
Frequency Multiplication by the PLL 1-12
G
GC0-GC3 (GPIOR Control Bits) 7-4
GD0-GD3 (GPIOR Data Bits) 7-4
GDD0-GDD3 (GPIOR Data Direction Bits) 7-4
General Purpose I/O — See Section 7
General Purpose I/O (GPIO) 1-19
General Purpose I/O Signal Descriptions 2-21
General Purpose Input/Output (GPIO) 1-10
GPIO
Circuit Diagram 7-5
Control/Data Register 7-3
GPIOR
Control Bits 7-4
Data Bits 7-4
Data Direction Bits 7-4
Pin Definition 7-4
Programming Model 7-3
GPIO (General Purpose I/O) 1-19
Ground 2-5
PLL 2-5
H
HA1, HA3-HA6 (HSAR I2C Slave Address) 5-9
HBER (HCSR Bus Error) 5-18
HBIE (HCSR Bus Error Interrupt Enable) 5-16
HBUSY (HCSR Host Busy) 5-19
HCKR (SHI Clock Control Register) 5-9
HCSR
Receive Interrupt Enable Bits 5-17
SHI Control/Status Register 5-13
HDM0-HDM5 (HCKR Divider Modulus
Select) 5-12
HEN (HCSR SHI Enable) 5-13
,
,
4-57
MOTOROLA