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Receiver Relative Timing (RREL)
Programming 6-14
Registers 6-8
Single Interrupt To Service Receiver And
Transmitter 6-24
TCS
Transmitter 0 Enable 6-17
Transmitter 1 Enable 6-17
Transmitter 2 Enable 6-18
Transmitter Clock Polarity 6-19
Transmitter Data Shift Direction 6-18
Transmitter Data Word Expansion 6-20
Transmitter Interrupt Enable 6-21
Transmitter Interrupt Location 6-22
Transmitter Left Data Empty 6-22
Transmitter Left Right Selection 6-19
Transmitter Master 6-18
Transmitter Relative Timing 6-20
Transmitter Right Data Empty 6-23
Transmitter Word Length Control 6-18
Transmit Data Registers 6-23
Transmit Section 6-6
Transmit Section Block Diagram 6-7
Transmitter Clock Polarity
Programming 6-20
Transmitter Control/Status Register
(TCS) 6-17
Transmitter Data Shift Direction
Programming 6-19
Transmitter Data Word Expansion
Programming 6-21
Transmitter Left Right Selection
Programming 6-19
Serial Audio Interface — See Section 6
Serial Audio Interface (SAI) 1-10
Serial Audio Interface (SAI) Receiver
signals 2-18
Serial Audio Interface (SAI) Transmitter
signals 2-20
Serial Audio Interface Signal Descriptions 2-18
Serial Host Interface (SHI) 1-10
Serial Host Interface (SHI) signals 2-14
Serial Host Interface—See Section 5
Serial Peripheral Interface Bus 1-18
,
SHI 1-18
5-3
Block Diagram 5-4
Clock Control Register—DSP Side 5-9
Clock Generator 5-5
Control/Status Register—DSP Side 5-13
Data Size 5-14
Exception Priorities 5-7
MOTOROLA
,
,
1-19
6-3
SHI Noise Reduction Filter Mode 5-12
Single Delay Line C-5
Single Delay Line Application C-5
Slow Read or Write DRAM Access Timing 4-58
SPI 1-18
,
,
1-18
5-3
,
5-3
DSP56009 User's Manual
HCKR
Clock Phase and Polarity Controls 5-10
Divider Modulus Select 5-12
Prescaler Rate Select 5-11
HCKR Filter Mode 5-12
HCSR
Bus Error Interrupt Enable 5-16
FIFO Enable Control 5-14
Host Request Enable 5-15
Idle 5-15
Master Mode 5-14
Serial Host Interface I2C/SPI
Selection 5-13
Serial Host Interface Mode 5-14
SHI Enable 5-13
Host Receive Data FIFO—DSP Side 5-9
Host Transmit Data Register—DSP Side 5-8
HREQ
Function In SHI Slave Modes 5-15
HSAR
I2C Slave Address 5-9
Slave Address Register 5-9
I/O Shift Register 5-8
Input/Output Shift Register—Host Side 5-8
Internal Architecture 5-4
Internal Interrupt Priorities 5-7
Interrupt Vectors 5-7
Introduction 5-3
Operation During Stop 5-31
Programming Considerations 5-23
Programming Model 5-5
Programming Model—DSP Side 5-6
Programming Model—Host Side 5-5
Slave Address Register—DSP Side 5-9
,
,
,
,
4-59
4-60
4-61
4-62
4-63
,
,
5-3
5-19
HCSR
Bus Error 5-18
Host Busy 5-19
Host Receive FIFO Full 5-18
Host Receive FIFO Not Empty 5-18
Host Receive Overrun Error 5-18
Host Transmit Data Empty 5-17
Host Transmit Underrun Error 5-17
Receive Interrupt Enable 5-16
Master Mode 5-25
Slave Mode 5-24
S
,
Index-5
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