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Programming Reference
Application:
S.A.I.
TCKP Description
0
Polarity is negative
1
Polarity is positive
TREL
Description
0
WSR occurs with 1st bit
1
WSR occurs 1 cycle earlier
TDWE Description
0
Last bit transmitted 8 times
1
First bit transmitted 8 times
TXIE
Description
0
Transmitter interrupts disabled
1
Transmitter interrupts enabled
TXIL
Description
0
Tx interrupt vector location at $1x
1
Tx interrupt vector location at $4x
TLDE
Description—Read Only
0
Left data register full
1
Left data register empty
TRDE Description—Read Only
0
Right data register full
1
Right data register empty
23
= Reserved, write as 0
*
Figure B-14 SAI Transmitter Control/Status Register (TCS)
B-26
16
15 14 13 12 11 10
*
*
TRDE
TLDE
TXIL
0
0
Transmitter Control/
DSP56009 User's Manual
Date:
Programmer:
TLRS
Description
0
WST low identifies Left data word;
WST high identifies Right data word
1
WST high identifies Left data word;
WST low identifies Right data word
TDIR
0
1
TWL1 TWL0 Number of Bits/Word
0
0
1
1
T0EN
Description
0
Transmitter 0 disabled
1
Transmitter 0 enabled
T1EN
Description
0
Transmitter 1 disabled
1
Transmitter 1 enabled
T2EN
Description
0
Transmitter 2 disabled
1
Transmitter 2 enabled
TMST Description
0
SAI slave
1
SAI master
9
8
7
6
TXIE
TDWE
TREL
TCKP
TLRS
TDIR
Status Register (TCS)
Sheet 2 of 4
Description
Data shifted out MSB first
Data shifted out LSB first
0
16
1
24
0
32
1
Reserved
5
4
3
2
1
TWL1
TWL0
TMST
T2EN
T1EN
X:$FFE4 Reset = $0000
MOTOROLA
0
T0EN
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