Motorola DSP56009 User Manual page 7

SECTION 4
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.1 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.1.2 EMI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2 EMI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.1 EMI Base Address Registers (EBAR0 and EBAR1) . . . . . 4-7
4.2.2 EMI Write Offset Register (EWOR) . . . . . . . . . . . . . . . . . . 4-7
4.2.3 EMI Offset Register (EOR) . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.4 EMI Data Write Registers (EDWR) . . . . . . . . . . . . . . . . . . 4-9
4.2.5 EMI Data Read Register (EDRR) . . . . . . . . . . . . . . . . . . . 4-9
4.2.6 EMI Data Register Buffer (EDRB) . . . . . . . . . . . . . . . . . . . 4-9
4.2.7 EMI Control/Status Register (ECSR). . . . . . . . . . . . . . . . 4-10
4.2.7.1 EMI Data Bus Width (EBW)-Bit 0 . . . . . . . . . . . . . . . 4-10
4.2.7.2 EMI Word Length (EWL[2:0])-Bits 16,2, and 1 . . . . . 4-11
4.2.7.3 EMI Addressing Mode (EAM[3:0])-Bits 6-3 . . . . . . . 4-12
4.2.7.4 EMI Increment EBAR After Read (EINR)-Bit 7 . . . . . 4-16
4.2.7.5 EMI Increment EBAR After Write (EINW)-Bit 8 . . . . 4-16
4.2.7.6 EMI Interrupt Select (EIS[1:0])-Bits 9-10 . . . . . . . . . 4-17
4.2.7.7 EMI Memory-Wrap Interrupt Enable
(EMWIE)-Bit 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.2.7.8 EMI Data Write Register Empty (EDWE)-Bit 12 . . . . 4-18
4.2.7.9 EMI Data Read Register Full (EDRF)-Bit 13 . . . . . . 4-18
4.2.7.10 EMI Data Register Buffer and Data Read Register
Full (EBDF)-Bit 14. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.2.7.11 EMI Busy (EBSY)-Bit 15 . . . . . . . . . . . . . . . . . . . . . . 4-19
4.2.7.12 EMI Read Trigger Select (ERTS)-Bit 17 . . . . . . . . . . 4-19
4.2.7.13 EMI DRAM Memory Timing (EDTM)-Bit 18 . . . . . . . 4-19
4.2.7.14 EMI SRAM Memory Timing
(ESTM[3:0])- Bits 19-22 . . . . . . . . . . . . . . . . . . . . . . 4-20
4.2.7.15 EMI Enable (EME)-Bit 23 . . . . . . . . . . . . . . . . . . . . . 4-21
4.2.8 EMI Refresh Control Register (ERCR) . . . . . . . . . . . . . . 4-21
4.2.8.1 EMI Refresh Clock Divider (ECD[7:0])-Bits 0-7 . . . . 4-22
4.2.8.2 ERCR Reserved Bits-Bits 8-17, 21 . . . . . . . . . . . . . 4-22
4.2.8.3 EMI Refresh Clock Prescaler
(EPS[1:0])-Bits 18-19. . . . . . . . . . . . . . . . . . . . . . . . 4-22
4.2.8.4 EMI One-Shot Refresh (EOSR)-Bit 20 . . . . . . . . . . . 4-22
MOTOROLA
EXTERNAL MEMORY INTERFACE . . . . . . . . . . . . 4-1
DSP56009 User's Manual v