Table 3-2 Internal I/O Memory Map - Motorola DSP56009 User Manual

Memory, Operating Modes, and Interrupts
DSP56009 Data And Program Memory Maps
Location
X: $FFFF
X: $FFFE
X: $FFFD
X: $FFFC
X: $FFFB
X: $FFFA
X: $FFF9
X: $FFF8
X: $FFF7
X: $FFF6
X: $FFF5
X: $FFF4
X: $FFF3
X: $FFF2
X: $FFF1
X: $FFF0
X: $FFEF
X: $FFEE
X: $FFED
X: $FFEC
X: $FFEB
X: $FFEA
X: $FFE9
X: $FFE8
X: $FFE7
X: $FFE6
X: $FFE5
X: $FFE4
X: $FFE3
X: $FFE2
X: $FFE1
X: $FFE0
X: $FFDF
3-10

Table 3-2 Internal I/O Memory Map

Register
Interrupt Priority Register (IPR)
Reserved
PLL Control Register (PCTL)
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO Control/Data Register (GPIOR)
EMI Write Offset Register (EWOR)
Reserved
Reserved
SHI Receive FIFO/Transmit Register (HRX/HTX)
2
SHI I C Slave Address Register (HSAR)
SHI Host Control/Status Register (HCSR)
SHI Host Clock Control Register (HCKR)
EMI Refresh Control Register (ERCR)
EMI Data Register 1 (EDRR1/EDWR1)
EMI Offset Register 1 (EOR1)
EMI Base Address Register 1 (EBAR1)
EMI Control/Status Register (ECSR)
EMI Data Register 0 (EDRR0/EDWR0)
EMI Offset Register 0 (EOR0)
EMI Base Address Register 0 (EBAR0)
SAI TX2 Data Register (TX2)
SAI TX1 Data Register (TX1)
SAI TX0 Data Register (TX0)
SAI TX Control/Status Register (TCS)
SAI RX1 Data Register (RX1)
SAI RX0 Data Register (RX0)
SAI RX Control/Status Register (RCS)
SAI Baud Rate Control Register (BRC)
Reserved
DSP56009 User's Manual MOTOROLA